Remote-control operating system and method for selectively addressing code-addressable receivers, particularly to execute switching function in automotive vehicles

Claim 2

Method of remotely controlling operation of a remote-control operating system for selective addressing and control of one of a plurality of receivers (11, 12) from a central station (10), particularly to selectively address and control operation of accessory apparatus or devices (16, 17-20) in a motor vehicle, having a data input unit (27, 25), including operating switches (29) associated with respective apparatus or devices to address the respective apparatus or devices; a data receiver and display unit (28) to display the state of an addressed apparatus or device; a ring bus (X, 15), all the respective receivers associated with respective apparatus or devices being connected to said ring bus; code generating and recognition means (10, 10a) connected to the data input unit and to the ring bus, and hence to the receivers, for generating codes representative of one of the receivers, of a function thereof, and decoding data transmitted by the receivers indicative of execution of a decoded operation or command; and decoding means (37, 44, 45, 38, 55) and code generating means (64) included in the receivers, responding to a characteristic pulse arrangement representative of a code assigned to the respective receivers, comprising connecting the ring bus as a closed loop single communication line (X, 15) and connecting said code generating and recognition means (10, 10a) and all the receivers (11, 12) in parallel to the ring bus; generating, in the code generation and recognition means, cyclically recurring binary pulse sequences which comprise clock (B) and synchronizing signals (C), and data or control signals (A, 0, 1); generating in the receiver acknowledgment code signals (B'), wherein said signal generating steps comprise coding said cyclically recurring binary pulse sequences by generating (1) a synchronizing and clock signal combination which comprises a first pulse (B) and a subsequent pulse gap having a first and long time duration (C, C'); (2) data or control signals which comprise (i) pulses (A, A') (1, 2, 3 . . . ) of a first predetermined pulse length to denote pulses being transmitted in a first direction between the code generating and recognition means and one of said receivers, and (ii) pulse gaps (a) between said pulses which have two different second and third gap lengths in dependence on whether the pulse gaps are representative of a binary ZERO or a binary ONE, both said pulse gaps being short with respect to said first long time duration, and (iii) pulses (B') of a second predetermined pulse length to denote pulses being transmitted in reverse direction between the code generating and recognition means and one of said receivers; and transmitting all said coded signal pulses with the respective pulse lengths and pulse gaps between the transmitter and receiver over said closed loop single communication line (X, 15) and forming said ring bus.

Claim 3

Method according to claim 1, wherein the ring bus comprises a light guide (15); and wherein the generating steps comprise generating light signals in the form of light pulses of respectively different pulse widths, with respectively different gaps between the pulses and optically coupling said pulses to the light guide.

Claim 4

Method according to claim 1, including the step of decoding in the receivers the duration of respective pulses and pulse gaps, by comparing the time of duration of respective pulses and respective pulse gaps with a time reference formed by the clock signals (B).

Claim 5

Method according to claim 3, wherein the time duration of pulse gaps of a first gap length is representative of a binary 0, and of a different gap length is representative of a binary 1; and a gap length which differs from either the gap length representative of binary 0 and binary 1 by a multiple of the extreme gap length representing binary 0 or binary 1 is representative of a new cycle of the cyclically recurring pulse sequences (A).

Claim 6

Method according to claim 4, wherein the step of generating an acknowledgment signal comprises changing the pulse width from that determined by a reference (clock B) by extending the width of one of the pulses of the pulse sequence to thereby place on the ring bus (X, 15) a signal which is modified by the receiver with respect to the signal which is transmitted by the code generation and recognition means, the extended pulse being recognized in the code generating and recognition means (10, 10a) for actuation of the data receiver and display unit (28).

Claim 7

Method according to claim 1, further comprising the step of counting cycles of binary pulse sequences including said synchronization and clock signal combination and the data or control signals comprising pulses (A, A') (1, 2, 3 . . . ) of a first predetermined pulse length and pulse gaps (a) between said pulses of one of said predetermined second and third gap lengths; and if the particular decoded number within the binary pulse sequence and associated with a specific receiver, as determined by the specific count decoding stage, has been decoded to determine that the same receiver is to be addressed by the same code being transmitted, in succession, a number of times in accordance with a predetermined count number, then and only then generating said pulses (B') of said second predetermined pulse length; and only then controlling operation of the respective apparatus or device addressed in accordance with the code representative of the receiver associated with the selected apparatus or device.

Claim 8

Remote-control operating system for selectively addressing and controlling one of a plurality of receivers (11, 12), particularly for selective addressing and control of operation of accessory apparatus or devices (16, 17, 18, 19, 20) of a motor vehicle having a data input unit (27, 25) including operating switches (29) associated with respective apparatus or devices; a data receiver and display unit (28) to display the state of addressed apparatus or devices with which the receiver is associated; a ring bus (X, 15) to which all the receivers are connected; code generation and recognition means (10, 10a) connected to the data input unit (27), the data receiver and display unit (28) and to the ring bus (8, 15), and hence to the receivers (11, 12), for generating codes representative of one of the receivers, or of a function of one of the receivers, and decoding data re-transmitted by the receivers indicative of execution of a decoded operating command; and decoding means (37, 45, 38, 55) included in the receivers responding to a pulse arrangement representative of a code appearing on the ring bus (8, 15), wherein the ring bus comprises a closed loop single communication line X, 15; said code generating and recognition means (10, 10a) and all said receivers (11, 12) being connected in parallel to the ring bus; the code generation and recognition means generate a digital binary pulse code, coupled to the ring bus, which comprises cyclically recurring binary pulse sequences which include clock (B) and synchronizing signals (C), and data or control signals (A, 0, 1); the code generation and recognition means (10, 10a) comprises (1) means for generating a synchronizing (B) and clock (C) signal, in which said synchronizing and clock signal comprises a first pulse (B) and a subsequent pulse gap having a first and long time duration (C, C'); and (2) means for generating data or control signals which comprise (i) pulses (A, A'; 1, 2, 3 . . . ) of a first predetermined pulse length to denote pulses being transmitted in a first direction between the code generating and recognition means (10, 10a) and all said receivers (11, 12), and (ii) pulse gaps (a) between said pulses which have two different second and third lengths, in dependence on whether the pulse gaps are to represent a binary ZERO or a binary ONE, both said pulse gaps being short with respect to said first long time duration; the receivers include, each, code generating means (64) generating acknowledgment signals (B'), said acknowledgment signals comprising pulses of a second predetermined pulse length, to denote pulses being transmitted in reverse direction between the pulse generating and recognition means and one of said receivers; the closed loop single communication line (X, 15) carrying all the signals with the respective coding distinctions for addressing being represented by respective widths of pulses and gaps between pulses.

Claim 9

Remote-control operating system for selectively addressing and controlling one of a plurality of receivers (11, 12), particularly for selective addressing and control of operation of accessory apparatus or devices (16, 17, 18, 19, 20) of a motor vehicle having a data input unit (27, 25) including operating switches (29) associated with respective apparatus or devices; a data receiver and display unit (28) to display the state of addressed apparatus or devices with which the receiver is associated; a ring bus (X, 15) to which all the receivers are connected; code generation and recognition means (10, 10a) connected to the data input unit (27), the data receiver and display unit (28) and to the ring bus (8, 15), and hence to the receivers (11, 12), for generating codes representative of one of the receivers, or of a function of one of the receivers, and decoding data re-transmitted by the receivers indicative of execution of a decoded operating command; and decoding means (37, 45, 38, 55) included in the receivers responding to a pulse arrangement representative of a code appearing on the ring bus (8, 15), wherein the ring bus comprises a closed loop single communication line X, 15; said code generating and recognition means (10, 10a) and all said receivers (11, 12) being connected in parallel to the ring bus; the code generation and recognition means generate a digital binary pulse code, coupled to the ring bus, which comprises cyclically recurring binary pulse sequences which include clock (B) and synchronizing signals (C), and data or control signals (A, 0, 1); the code generation and recognition means (10, 10a) comprises (1) means for generating a synchronizing (B) and clock (C) signal, in which said synchronizing and clock signal comprises a first pulse (B) and a subsequent pulse gap having a first and long time duration (C, C'); and (2) means for generating data or control signals which comprise (i) pulses (A, A'; 1, 2, 3 . . . ) of a first predetermined pulse length to denote pulses being transmitted in a first direction between the code generating and recognition means (10, 10a) and all said receivers (11, 12), and (ii) pulse gaps (a) between said pulses which have two different second and third lengths, in dependence on whether the pulse gaps are to represent a binary ZERO or a binary ONE, both said pulse gaps being short with respect to said first long time duration; the receivers include, each, code generating means (64) generating acknowledgment signals (B'), said acknowledgment signals comprising pulses of a second predetermined pulse length, to denote pulses being transmitted in reverse direction between the pulse generating and recognition means and one of said receivers; the closed loop single communication line (X, 15) carrying all the signals with the respective coding distinctions for addressing being represented by respective widths of pulses and gaps between pulses.

Claim 10

System according to claim 7, wherein said single communication line comprises a light guide (15) carrying said recurring pulse sequences (A) in the form of light pulse sequences being transmitted between the code generation and recognition means (10, 10a) and all of said receivers (11, 12, 12a).

Claim 11

System according to claim 8, further including light branching and coupling stations (21) positioned to transfer light signals between the code generation and recognition means (10), the light guide (15), and between the receivers (11, 12) and the light guide; and wherein said branching and coupling stations (21) include opto-electrical transducers (22, 23; 35, 36) to convert the light pulses in the light guide to electrical signals.

Claim 12

System according to claim 9, wherein the opto-electrical transducers at said branching and coupling stations (21) include optical-electrical receivers (23, 35) to receive light signals coursing in the light guide, and opto-electrical transmitters (22, 66) to transmit light pulses in accordance with applied electrical signals into the light guide for coursing in the form of light pulses therein.

Claim 13

System according to claim 9, wherein the branching and coupling stations include a light guide fiber (24) having a mirrored end surface (24a), the mirrored end surface being coupled to the light guide (15) to form an angle with respect to the longitudinal axis (X) of the light guide.

Claim 14

System according to claim 11, wherein the light guide fiber (24) terminates at a position adjacent said opto-electrical transducers; and said transducers include a photo diode (35) and a light emitting diode (66).

Claim 15

System according to claim 9, wherein at least one of the receivers (12) forms a receiving station having a plurality of receiver units (12a) included therein, said receiver units being commonly coupled to a single branching and coupling station (21).

Claim 16

System according to claim 7, wherein the decoding means in the receiver are responsive to the duration of pulse gaps and include a pulse counter (37) having a reset (R) input, the count input of the pulse counter being connected to receive pulses from said single communication line; a reset circuit (38) coupled to receive pulses from said single communication line, and including a timing circuit (40, 42) responsive to a first, and long gap between recurring pulses, to sense the beginning and presence of one of the cyclically recurring pulse sequences (A) coursing in the single communication line forming the ring bus, and being connected to the reset terminal of the pulse counter to reset the pulse counter to a predetermined value upon failure to sense occurrence of pulses, for said first and long predetermined interval on the ring bus; a count decoding stage (44, 45) coupled to the pulse counter (37) and connected to recognize a predetermined count number being counted by the pulse counter after having been reset; and operating circuit means (50, 51) connected to the respective device, and controlled by the output from said pulse counter to energize said pulse counter if, and only if, the count number designed to the particular apparatus or device is recognized by the count decoding stage.

Claim 17

System according to claim 14, wherein the decoding means in the receiver further include a gap timing circuit (55) connected to receive the pulses of the cyclically recurring pulse sequence and providing an output signal (0, 1) representative of the time interval or gap between pulses to recognize a code formed by making the gap between recurring pulses within the predetermined pulse sequence longer than between other pulses to thus characterize the particular selected pulse.

Claim 18

System according to claim 15, wherein the decoding means further includes a conjunctive gate (47) having the output from said count decoding stage (44, 45) applied thereto and from said gap timing circuit (55) if the gap timing circuit has recognized an extended pause representative of a 1-signal between the pulse recognized by the count decoding stage and the next succeeding pulse.

Claim 19

System according to claim 14, further including a pulse sequence cycle counter (48) connected between the output of the count decoding stage (44, 45) decoding the outputs from the pulse counter (37) and said operating circuit means (50, 51), said cycle counter providing an output to the operating circuit means if, and only if, the particular decoded number associated with the specific receiver as determined by the specific count decoding stage has determined that the same receiver is to be addressed by the same code being transmitted, in succession, a number of times in accordance with the count number of the cycle counter.

Claim 20

System according to claim 16, further including a pulse sequence cycle counter (48) connected between the output of the count decoding stage (44, 45) decoding the outputs from the pulse counter (37) and said operating circuit means (50, 51), said cycle counter providing an output to the operating circuit means if, and only if, the particular decoded number associated with the specific receiver as determined by the specific count decoding stage has determined that the same receiver is to be addressed by the same code being transmitted, in succession, a number of times in accordance with the count number of the cycle counter; and wherein the cycle counter is connected to and controlled by the output from the conjunctive gate (47).

Claim 21

System according to claim 18, further including an inverter stage (54) connected to the output of the cycle counter and additionally connected to the conjunctive gate (47) to inhibit further counting of the cycle counter after it had once counted through the predetermined number of cycles.

Claim 22

System according to claim 18, including logic circuit means (60, 61) connected to and controlled by the output (f) from the gap timing circuit (55) and controlling resetting of the cycle counter (48).

Claim 23

System according to claim 7, wherein the means for generating the pulses of a second predetermined pulse length in the receiver includes acknowledgment circuit means (30) providing an acknowledgment output signal representative of response of the device or apparatus in accordance with an addressed command transmitted from said data input unit through the code generating means; an acknowledgment timing means (64), the output of said acknowledgment timing means being connected to provide an extension signal to said single communication line forming the ring bus, said acknowledgment timing means being connected to and controlled by operation of a device to provide a timing pulse when the decoding means in the receiver recognizes the presence of a particular pulse in said cyclically recurring pulse sequence and associated with a specific receiver, to thereby extend the length of said pulse coursing in the ring bus and permit recognition of the extended pulse by the code generation and recognition means (10, 10a) in the central station, and thus permit display by the data receiver and display unit (28) that the addressed apparatus or device has received the addressing command.

Claim 24

System according to claim 14, further including an acknowledgment circuit means (30) providing an acknowledgment output signal representative of the apparatus or device having been properly addressed and carrying out the command as instructed by the data input unit; and an acknowledgment timing means (64) comprising a monostable circuit (64) controlled from the output (g) of the count decoding stage, the output of said acknowledgment timing means being connected to apply a signal to the single communication line (15) of the ring bus (8) to thereby extend the length of the pulse decoded by the count decoding stage and permit recognition of said extension of said decoded pulse by the code generating and recognition means (10) in the central station for display of acknowledgment of the operating command on the data receiver and display unit (28).

Claim 25

System according to claim 22, wherein said single communication line comprises a light guide; and wherein the output of said acknowledgment timing means (64) is coupled to light emitting element (66) to extend a light pulse occurring within said light guide and forming the pulse decoded by the decoding means (44, 45) in the receiver, to thus, by continued application of light to said light guide, extend the length of said pulse.

Claim 26

System according to claim 19 or 20, wherein said single communication line (15) comprises a light guide.