Digital synchronization technique

Claim 2

For use with a data communications receiving-end modem, digital synchronization apparatus, comprising: sampling means, for sampling at a fixed sampling rate a data signal that was transmitted at a baud rate not necessarily in synchronism with the sampling rate; buffer means, for temporarily storing signal samples derived from said sampling means; interpolation means, coupled to said buffer means, for providing to the modem an interpolated sequence of signal samples effectively synchronized with the data signal baud rate; baud synchronization detection means, for detecting whether the interpolated sequence of signal samples supplied to the modem is in synchronism with the baud rate; and timing and control means, for controlling operation of said buffer means and said interpolation means in response to signals from said baud synchronization detection means, to maintain the interpolated sequence of signal samples substantially in synchronism with the baud rate.

Claim 3

Digital synchronization apparatus as set forth in claim 1, wherein: said baud synchronization means generates an early/late signal indicative of whether the interpolated sequence of signal samples applied to the modem are early or late with respect to the baud rate; said timing and control means includes an up-down counter for registering an accumulated interpolation delay indicative of the accumulated relative delay between the sampling rate and the baud rate, by counting up or down in response to the early/late signal; and said interpolation means includes an interpolation filter having filter coefficients provided by said timing and control means.

Claim 4

Digital synchronization apparatus as set forth in claim 2, wherein: said buffer means includes means for generating a repeated sample on command and means for skipping a sample on command; said up-down counter includes means for generating an overflow signal and an underflow signal whenever the contents of said counter overflows or underflows; and the overflow and underflow signals are coupled to said buffer means, to provide for a repeated sample or a skipped sample in the event that the contents of said up-down counter overflows or underflows.

Claim 5

Digital synchronization apparatus as set forth in claim 2, wherein: said timing and control means further includes means coupled to said up-down counter, for selecting a new set of filter coefficients in response to a change in the accumulated interpolation delay registered in said up-down counter.

Claim 6

Digital synchronization apparatus as set forth in claim 3, wherein: said timing and control means further includes means coupled to said up-down counter, for selecting a new set of filter coefficients in response to a change in the accumulated interpolation delay registered in said up-down counter.

Claim 7

Digital synchronization apparatus as set forth in claim 4 wherein: said interpolation filter has two stages; and said means coupled to said up-down counter includes a subtraction circuit, and derives a first filter coefficient from the contents of said counter and a second filter coefficient from the difference between unity and the contents of said counter, as determined in said subtraction circuit.

Claim 8

Digital synchronization apparatus as set forth in claim 5, wherein: said interpolation filter has two stages; and said means coupled to said up-down counter includes a subtraction circuit, and derives a first filter coefficient from the contents of said counter and a second filter coefficient from the difference between unity and the contents of said counter, as determined in said subtraction circuit.

Claim 9

Digital synchronization means as set forth in claim 4, wherein: said interpolation filter has more than two stages; and said means coupled to said up-down counter includes a read-only memory for storage of n sets of filter coefficients, where n is the number of possible states of said counter, and means for retrieving a set of filter coefficients from said read-only memory in response to a change in the state of said counter.

Claim 10

Digital synchronization means as set forth in claim 5, wherein: said interpolation filter has more than two stages; and said means coupled to said up-down counter includes a read-only memory for storage of n sets of filter coefficients, where n is the number of possible states of said counter, and means for retrieving a set of filter coefficients from said read-only memory in response to a change in the state of said counter.

Claim 11

For use with a data communications receiving-end modem, digital synchronization apparatus, comprising: an analog-to-digital converter for converting to digital form samples of a data signal received at baud rate determined at a remote transmitter; a fixed-frequency oscillator for controlling said converter to provide digital signal samples at a fixed sampling rate not necessarily in synchronism with the signal baud rate; a buffer register for temporarily storing the digital signal samples on a first-in-first-out basis; an interpolation filter connected to receive as inputs temporarily stored signal samples from said buffer register, and to provide as outputs to a modem interpolated signal samples that are effectively synchronized with the data signal baud rate; baud synchronization detection means, for detecting whether the interpolated signal samples supplied to the modem are in synchronism with the baud rate, and for generating an early/late signal to indicate whether the interpolated signals are early or late with respect to the baud rate; an up-down counter for registering an accumulated interpolation delay in response to the early/late signals applied to increment or decrement the contents of said counter; and means coupled to said up-down counter, for selecting a new set of interpolation filter coefficients in response to a change in the accumulated interpolation delay registered in said up-down counter.

Claim 12

For use with a data communications receiving-end modem, digital synchronization apparatus, comprising: an analog-to-digital converter for converting to digital form samples of a data signal received at baud rate determined at a remote transmitter; a fixed-frequency oscillator for controlling said converter to provide digital signal samples at a fixed sampling rate not necessarily in synchronism with the signal baud rate; a buffer register for temporarily storing the digital signal samples on a first-in-first-out basis; an interpolation filter connected to receive as inputs temporarily stored signal samples from said buffer register, and to provide as outputs to a modem interpolated signal samples that are effectively synchronized with the data signal baud rate; baud synchronization detection means, for detecting whether the interpolated signal samples supplied to the modem are in synchronism with the baud rate, and for generating an early/late signal to indicate whether the interpolated signals are early or late with respect to the baud rate; an up-down counter for registering an accumulated interpolation delay in response to the early/late signals applied to increment or decrement the contents of said counter; and means coupled to said up-down counter, for selecting a new set of interpolation filter coefficients in response to a change in the accumulated interpolation delay registered in said up-down counter.

Claim 13

Digital synchronization apparatus as set forth in claim 10, wherein: said buffer register includes means for generating a repeated sample on command and means for skipping a sample on command; said up-down counter includes means for generating an overflow signal and an underflow signal whenever the contents of said counter overflows or underflows; and the overflow and underflow signals are coupled to said buffer register, to provide for a repeated sample or a skipped sample in the event that the contents of up-down counter overflows or underflows.

Claim 14

Digital synchronization apparatus as set forth in claim 10, wherein: said interpolation filter has two stages; and said means coupled to said up-down counter includes a subtraction circuit, and derives a first filter coefficient from the contents of said counter and a second filter coefficient from the difference between unity and the contents of said counter, as determined in said subtraction circuit.

Claim 15

Digital synchronization apparatus as set forth in claim 11, wherein: said interolation filter has two stages; and said means coupled to said up-down counter includes a subtraction circuit, and derives a first filter coefficient from the contents of said counter and a second filter coefficient from the difference between unity and the contents of said counter, as determined in said subtraction circuit.

Claim 16

Digital synchronization apparatus as set forth in claim 10, wherein: said interpolation filter has more than two stages; and said means coupled to said up-down counter includes a read-only memory for storage of n sets of filter coefficients, where n is the number of possible states of said counter, and means for retrieving a set of filter coefficients from said read-only memory in response to a change in the state of said counter.

Claim 17

Digital synchronization apparatus as set forth in claim 11, wherein: said interpolation filter has more than two stages; and said means coupled to said up-down counter includes a read-only memory for storage of n sets of filter coefficients, where n is the number of possible states of said counter, and means for retrieving a set of filter coefficients from said read-only memory in response to a change in the state of said counter.

Claim 22

A method as set forth in claim 17, wherein: said accumulating step includes incrementing or decrementing a counter, the contents of which represents the accumulated delay index; and said selecting step includes retrieving the appropriate coefficients from a read-only memory.