Clock control of a central processing unit from a monitor interface unit

Claim 1

A data processing system includes a plurality of subsystems, a main memory, a central processor unit (CPU), a cache and a plurality of I/O controllers, all coupled in common to a system bus, said CPU also being coupled to said cache by a separate bus, a monitor interface unit is coupled to said system bus, said cache by a cache bus and said CPU by a CPU bus for monitoring information transferred over said system bus, information transferred between said CPU and said cache and internal CPU information, a monitor is coupled to said monitor interface unit for receiving hit signals indicative of predetermined information for generating data processing system performance data, apparatus in said monitor interface unit generates a stop clock signal having a fixed predetermined cycle time, said stop clock signal being applied to said CPU via said CPU bus, said CPU having clock control means responsive to states of said stop clock signal for starting and stopping a CPU clock signal resulting in a CPU clock signal cycling at said fixed predetermined cycle time which causes the starting or stopping of the CPU operation, said apparatus comprising: a mode switch for generating a clock stop enable signal; first one-shot multivibrator means responsive to said CPU clock signal, said clock stop enable signal and a potentiometer resistance value setting for generating a first and a second stretched pulse signal wherein said first and said second stretched pulse signals are complementary signals; first latch means responsive to said CPU clock signal and said first stretched pulse signal for setting an output of said first latch means to a first state; second one-shot multivibrator means responsive to said second stretched pulse signal for generating a delayed stretched pulse signal; second latch means responsive to said clock stop enable signal, said delayed stretched pulse signal and said second stretched pulse signal for generating a stop reset signal, said first latch means being responsive to said stop reset signal for setting said output to a second state; third latch means enabled by a reset switch signal and responsive to the generation of a predetermined hit signal for setting an output of said third latch means to a first state; and NOR gate means responsive to said outputs of said first and third latch means for generating said stop clock signal to said CPU.