US4425643A
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US
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Multi-speed logic analyzer
Assignee: Tektronix Inc
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Filing: 1981-06-08
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Granted: 1984-01-10
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Expires: 2001-06-08
Abstract
Abstract A logic analyzer which can simultaneously measure one block of input data in detail and the same or another block of input data in rough form is disclosed. The logic analyzer comprises first and second sections each including a memory circuit to store the input data and a word recognizer to detect the desired trigger word from the input data. These first and second sections receive different clocks having different rates, and the second memory circuit stores the first clock applied to said first section for recognizing the time relationship of these clock signals. A counter counts the first clock in accordance with the outputs from the first and second word recognizers for recognizing the time relationship of the first and second trigger words.
Inventors
- 👤 David D. Chapman
- 👤 Gerd H. Hoeren
- 👤 Steven R. Palmquist
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:04
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3177; G06; G06F; G06F11/00; G06F11/22; G06F11/25
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
118 words
A multi-speed logic analyzer, comprising: first and second logic analyzer sections each including a memory circuit to store input data and a word recognizer to detect a predetermined word from said input data for controlling said memory circuit; and a counter to count a clock signal in accordance with the outputs from said word recognizers of said first and second logic analyzer sections, wherein said counter starts to count when said word recognizer of said first logic analyzer section detects a first predetermined word and stops counting when said word recognizer of said second logic analyzer section detects a second predetermined word; wherein clock signals for said first and second logic analyzer sections are different from each other.
Claim 2
Dependent Claim
118 words
A multi-speed logic analyzer, comprising: first and second logic analyzer sections each including a memory circuit to store input data and a word recognizer to detect a predetermined word from said input data for controlling said memory circuit; and a counter to count a clock signal in accordance with the outputs from said word recognizers of said first and second logic analyzer sections, wherein said counter starts to count when said word recognizer of said first logic analyzer section detects a first predetermined word and stops counting when said word recognizer of said second logic analyzer section detects a second predetermined word; wherein clock signals for said first and second logic analyzer sections are different from each other.
Claim 3
Dependent Claim
29 words
A logic analyzer according to claim 1 wherein said second logic analyzer section further comprises means for receiving and storing said clock signal for said first logic analyzer section.
Claim 4
Dependent Claim
80 words
A logic analyzer according to claim 1 further comprising a first input channel for said first logic analyzer section and a second input channel for said second logic analyzer section, wherein said second logic analyzer section further includes a multiplexer the inputs of which are coupled to both said first and second input channels and the output of which is coupled to said memory circuit and word record recognizer of said second logic analyzer section to select the input data.
Claim 5
Dependent Claim
40 words
A logic analyzer according to claim 1 further comprising a central processing unit and firmware stored in a read-only memory coupled to said memory circuits, said word recognizers, and said counter for controlling said first and second logic analyzer sections.
Claim 6
Dependent Claim
110 words
A multi-speed logic analyzer, comprising: first and second logic analyzer sections each including a memory circuit to store input data and a word recognizer to detect a predetermined word from said input data for controlling said memory circuit; a counter to count a clock signal in accordance with the outputs from said word recognizers of said first and second logic analyzer sections; and a display device for displaying the stored data in said memory circuits of said first and second logic analyzer sections, said display device also for displaying the content of said counter; wherein clock signals for said first and second logic analyzer sections are different from each other.
Claim 7
Dependent Claim
110 words
A multi-speed logic analyzer, comprising: first and second logic analyzer sections each including a memory circuit to store input data and a word recognizer to detect a predetermined word from said input data for controlling said memory circuit; a counter to count a clock signal in accordance with the outputs from said word recognizers of said first and second logic analyzer sections; and a display device for displaying the stored data in said memory circuits of said first and second logic analyzer sections, said display device also for displaying the content of said counter; wherein clock signals for said first and second logic analyzer sections are different from each other.
Claim 8
Dependent Claim
191 words
A logic analyzer, comprising: a first memory circuit to store input data under control of a first control circuit which receives a first clock signal; a first word recognizer for detecting a first predetermined word from input data applied to said first memory circuit and controlling said first control circuit; a second memory circuit to store said first clock signal and a selectable one of other input data and the same input data to be stored in said first memory circuit under control of a second control circuit which receives a second clock signal; a second word recognizer for detecting a second predetermined word from the input data applied to said second memory circuit and controlling said second control circuit; and a counter to count said first clock signal in accordance with the outputs from said first and second word recognizers, wherein said counter starts to count said first clock signal when said first word recognizer detects said first predetermined word and stops counting when said second word recognizer detects said second predetermined word; wherein the frequency of said first clock signal is different from that of said second clock signal.
Claim 9
Dependent Claim
191 words
A logic analyzer, comprising: a first memory circuit to store input data under control of a first control circuit which receives a first clock signal; a first word recognizer for detecting a first predetermined word from input data applied to said first memory circuit and controlling said first control circuit; a second memory circuit to store said first clock signal and a selectable one of other input data and the same input data to be stored in said first memory circuit under control of a second control circuit which receives a second clock signal; a second word recognizer for detecting a second predetermined word from the input data applied to said second memory circuit and controlling said second control circuit; and a counter to count said first clock signal in accordance with the outputs from said first and second word recognizers, wherein said counter starts to count said first clock signal when said first word recognizer detects said first predetermined word and stops counting when said second word recognizer detects said second predetermined word; wherein the frequency of said first clock signal is different from that of said second clock signal.
Claim 10
Dependent Claim
172 words
A logic analyzer, comprising: means for generating first and second clock signals wherein the rate of said first clock signal is lower than the rate of said second clock signal; a first logic analyzer section comprising a first input channel, a first memory device and a first word recognizer coupled to said first input channel, and a first memory control circuit coupled to said first memory device and being responsive to said first clock signal; a second logic analyzer section comprising a second input channel, a second memory device and a second word recognizer coupled to said second input channel, and a second memory control circuit coupled to said second memory device and being responsive to said second clock signal, said second memory also receiving for storage therein said first clock signal, and a counter for counting said slow clock signal, said counter receiving a word recognition signal from said first word recognizer as a start signal, and receiving a word recognition signal from said second word recognizer as a stop signal.
Claim 11
Dependent Claim
172 words
A logic analyzer, comprising: means for generating first and second clock signals wherein the rate of said first clock signal is lower than the rate of said second clock signal; a first logic analyzer section comprising a first input channel, a first memory device and a first word recognizer coupled to said first input channel, and a first memory control circuit coupled to said first memory device and being responsive to said first clock signal; a second logic analyzer section comprising a second input channel, a second memory device and a second word recognizer coupled to said second input channel, and a second memory control circuit coupled to said second memory device and being responsive to said second clock signal, said second memory also receiving for storage therein said first clock signal, and a counter for counting said slow clock signal, said counter receiving a word recognition signal from said first word recognizer as a start signal, and receiving a word recognition signal from said second word recognizer as a stop signal.
Claim 12
Dependent Claim
58 words
A logic analyzer in accordance with claim 7 wherein said first input channel is also applied to said second logic analyzer section, and wherein said second logic analyzer section further comprises a multiplexer coupled to both said first and second input channels thereby to selectively apply input data to said second memory device and said second word recognizer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-01-09 | 1987-07-11 | 1988-01-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-01-09 | 1991-07-11 | 1992-01-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-01-09 | 1995-07-11 | 1996-01-10 | $7700.00 | Window Closed / Lapsed |