US4423488A
Expired / Lapsed
US
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Digital filter employing PROM for storing positive and negative impulse response values
Assignee: Harris Corp
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Filing: 1981-01-09
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Granted: 1983-12-27
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Expires: 2001-01-09
Abstract
Abstract A digital filter, having a raised-cosine function in the frequency domain, is implemented in the time domain. For positive and negative impulse inputs, the time domain response of the corresponding frequency domain raised cosine response is created by way of a programmable read-only memory (PROM), the contents of which are selectively addressed by the combination of the contents of a shift register and a counter. The shift register contains a prescribed number of digital samples of successive data bits to be transmitted, while the counter is employed to identify or scan a plurality of successive finite filter response values, based upon the current contents of the shift register. From the memory locations of the PROM corresponding to successively generated address, values are read out representative of the overall or accumulated filter response attributable to the data bits stored in the shift register at the successive sample points determined by the contents of the counter.
Inventors
- 👤 David K. Campbell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 10:40
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
156 words
A digital filter comprising: first means for receiving and storing sequential values of an input binary data signal; second means coupled to said first means for producing a first clock signal in response to which said first means stores sequential values of said input binary data signal; third means for storing a plurality of filter output signal values each of which is representative of the sum of the values of individual positive and negative impulse response characteristics of a prescribed filter function for the sequential values of said input binary data signal stored by said first means, at each of a plurality of sampling points, over the signal value span stored thereby; and fourth means, coupled between said third means and said first and second means, for addressing said third means in accordance with the contents of said first and second means and thereby causing said third means to produce filter output signal values stored therein.
Claim 2
Dependent Claim
156 words
A digital filter comprising: first means for receiving and storing sequential values of an input binary data signal; second means coupled to said first means for producing a first clock signal in response to which said first means stores sequential values of said input binary data signal; third means for storing a plurality of filter output signal values each of which is representative of the sum of the values of individual positive and negative impulse response characteristics of a prescribed filter function for the sequential values of said input binary data signal stored by said first means, at each of a plurality of sampling points, over the signal value span stored thereby; and fourth means, coupled between said third means and said first and second means, for addressing said third means in accordance with the contents of said first and second means and thereby causing said third means to produce filter output signal values stored therein.
Claim 3
Dependent Claim
79 words
a digital filter according to claim 1, wherein: said second means includes means for receiving an input clock signal and producing therefrom said first clock signal, and wherein said fourth means includes means, coupled to said second means, for causing said third means to produce said filter output signal values in dependence upon sequential values stored by said first means and a prescribed relationship between said input clock signal and said first clock signal produced by said second means.
Claim 4
Dependent Claim
93 words
A digital filter according to claim 2, wherein: said second means includes counter means for counting input clock signals and producing said first clock signal upon counting a precribed number of said input clock signals, and wherein said third means comprises a read-only memory, the respective memory locations of which store said plurality of filter signal values, and wherein said fourth means includes mans for generating address signals for accessing said memory in accordance with the combination of the data values stored by said first means and the contents of said counter means.
Claim 5
Dependent Claim
108 words
A digital filter according to claim 3, wherein said first means comprises an N stage shift register into which a prescribed number of sequential values of said input binary data signal are coupled, and said counter comprises an R-stage binary counter for dividing the frequency fs of said input clock by R to produce said first clock signal by way of which sequential values of said input binary data signal are coupled into and through said shift register, the combination of the binary states of the stages of said shift register and the binary states of said R-stage binary counter defining respective addresses for accessing said read-only memory.
Claim 6
Dependent Claim
73 words
A digital filter according to claim 4, wherein each of the filter output signal values stored by said read-only memory is representative of the sum of sampled values of individual finite positive and negative impulse response characteristics for said prescribed filter function at each of the R sampling points for the N sequential values of said input binary data signal over the span of N data symbols stored by said N-stage shift register.
Claim 7
Dependent Claim
21 words
A digital filter according to claim 5, wherein said prescribed filter function has a raised-cosine filter characteristic in the frequency domain.
Claim 8
Dependent Claim
21 words
A digital filter according to claim 1, wherein said precribed filter function has a raised-cosine filter characteristic in the frequency domain.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-26 | 1987-06-27 | 1987-12-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-26 | 1991-06-27 | 1991-12-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-26 | 1995-06-27 | 1995-12-27 | $7700.00 | Window Closed / Lapsed |