US4420694A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Muting circuit
Assignee: Sony Corp
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Filing: 1981-07-22
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Granted: 1983-12-13
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Expires: 2001-07-22
Abstract
Abstract Disclosed is a muting circuit, in which the generation of click noise is prevented in that the muting operation is caused to occur at an instant when the instantaneous level (i.e., waveform level) of the input audio signal becomes zero for the first time since the appearance of a muting signal.
Inventors
- 👤 Teppei Yokota
- 👤 Yoshiro Joichi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:19
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/20; H03G3/30; H03G3/34; H03G3/341
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
110 words
A digital muting circuit comprising, an input terminal for receiving a PCM signal having words of plural bits, an output terminal for deriving said PCM signal, a controlling circuit for generating a muting signal, a detecting circuit for examining the bit pattern of said PCM signal to produce a detected signal when the signal level of the waveform corresponding to said PCM signal is less than a predetermined value, and switching means connected between said input terminal and said output terminal and for replacing said PCM signal with a PCM signal having a bit pattern representing the zero level by receiving said detected signal while said muting signal is generated.
Claim 2
Dependent Claim
110 words
A digital muting circuit comprising, an input terminal for receiving a PCM signal having words of plural bits, an output terminal for deriving said PCM signal, a controlling circuit for generating a muting signal, a detecting circuit for examining the bit pattern of said PCM signal to produce a detected signal when the signal level of the waveform corresponding to said PCM signal is less than a predetermined value, and switching means connected between said input terminal and said output terminal and for replacing said PCM signal with a PCM signal having a bit pattern representing the zero level by receiving said detected signal while said muting signal is generated.
Claim 3
Dependent Claim
72 words
A digital muting circuit according to claim 1, further comprising time counting means for counting a predetermined time elapsed from the instant of change of said muting signal and for producing a switching signal so as to cause the switching operation of said switching means on the basis of the relationship between the time elapsed from the instant of change of said muting signal and the waveform level of said input signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-12-12 | 1987-06-13 | 1987-12-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-12-12 | 1991-06-13 | 1991-12-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-12-12 | 1995-06-13 | 1995-12-13 | $7700.00 | Window Closed / Lapsed |