Distributed bus arbitration method and apparatus

Claim 2

In combination: a plurality of elements interconnected by an asynchronous common bus; each of said elements comprising arbitration means for determining bus priority of one element relative to another element, said arbitration means coupled to said common bus; each of said arbitration means comprising means coupled to said common bus for generating an arbitration code; said common bus comprising means for forming a composite complementary code from a plurality of said arbitration codes; and each of said arbitration means comprising means coupled to said common bus for decoding said composite complementary code for determining the priority of said element.

Claim 3

The combination as recited in claim 1 wherein: each of said elements includes a signal processor, a mass memory or an input-output controller.

Claim 4

The combination as recited in claim 1 wherein: said arbitration code comprises a series of bits and the complement of said bits.

Claim 5

The combination as recited in claim 1 wherein: said composite complementary code forming means comprises a wire-ORed bus.

Claim 6

In combination: a plurality of elements interconnected by an asynchronous common bus; each of said elements comprising arbitration means for determining the bus priority of one element relative to another element, said arbitration means coupled to said common bus; each of said arbitration means comprising means coupled to said common bus for generating an arbitration code; said common bus comprising means for forming a composite complementary code from a plurality of said arbitration codes; each of said arbitration means comprising means coupled to said common bus for decoding said composite complementary code for determining the priority of said element; and said arbitration means comprising arbitration control means coupled to said decoding means for synchronizing the formation of said composite complementary code on said bus.

Claim 7

In combination: a plurality of elements interconnected by an asynchronous common bus; each of said elements comprising arbitration means for determining the bus priority of one element relative to another element, said arbitration means coupled to said common bus; each of said arbitration means comprising means coupled to said common bus for generating an arbitration code; said common bus comprising means for forming a composite complementary code from a plurality of said arbitration codes; each of said arbitration means comprising means coupled to said common bus for decoding said composite complementary code for determining the priority of said element; and said arbitration means comprising arbitration control means coupled to said decoding means for synchronizing the formation of said composite complementary code on said bus.

Claim 8

The combination as recited in claim 5 wherein: each of said elements includes a signal processor, a mass memory or an input-output controller.

Claim 9

The combination as recited in claim 5 wherein: said arbitration code comprises a series of bits and the complement of said bits.

Claim 10

The combination as recited in claim 5 wherein: said composite complementary code forming means comprises a wire-ORed bus.

Claim 11

The combination as recited in claim 5 wherein: said decoding means further comprises means coupled to said arbitration control means for determining if said element is a lower priority element thereby removing said element's arbitration code from said bus.

Claim 12

The combination as recited in claim 5 wherein: each of said elements further comprises element address register means coupled to said decoding means and said common bus for changing an element's priority by changing the address of said element.

Claim 13

In combination: a plurality of elements interconnected by an asynchronous common bus; each of said elements comprising arbitration means for determining the bus priority of one element relative to another element, said arbitration means coupled to said common bus; each of said arbitration means comprising means coupled to said common bus for generating an arbitration code; said common bus comprising means for forming a composite complementary code from a plurality of said arbitration codes; each of said arbitration means comprising means coupled to said common bus for decoding said composite code; said arbitration means comprising arbitration control means coupled to said decoding means for synchronizing the formation of said composite complementary code on said bus; and said decoding means comprising means for generating a WIN signal to initiate transmitting information on said bus after arbitration is completed.

Claim 14

In combination: a plurality of elements interconnected by an asynchronous common bus; each of said elements comprising arbitration means for determining the bus priority of one element relative to another element, said arbitration means coupled to said common bus; each of said arbitration means comprising means coupled to said common bus for generating an arbitration code; said common bus comprising means for forming a composite complementary code from a plurality of said arbitration codes; each of said arbitration means comprising means coupled to said common bus for decoding said composite code; said arbitration means comprising arbitration control means coupled to said decoding means for synchronizing the formation of said composite complementary code on said bus; and said decoding means comprising means for generating a WIN signal to initiate transmitting information on said bus after arbitration is completed.

Claim 15

The combination as recited in claim 11 wherein: each of said elements includes a signal processor, a mass memory or an input-output controller.

Claim 16

The combination as recited in claim 11 wherein: said arbitration code comprises a series-of bits and the complement of said bits.

Claim 17

The combination as recited in claim 11 wherein: said composite complementary code forming means comprises a wire-ORed bus.

Claim 18

The combination as recited in claim 11 wherein: said decoding means further comprises means coupled to said arbitration control means for determining if said element is a lower priority element thereby removing said element's arbitration code from said bus.

Claim 19

The combination as recited in claim 11 wherein: each of said elements further comprises element address register means coupled to said decoder means and said common bus for changing an element's priority by changing the address of said element.

Claim 20

In combination: a plurality of elements interconnected by an asychronous common bus; means for generating a request in each of said elements to occupy said common bus; means coupled to said common bus in each of said elements for providing an element arbitration code for each of said elements; said common bus comprising means for performing a logical-OR of each bit of said element arbitration code on said bus for each of said elements forming a composite complementary code; means coupled to said common bus in each of said elements for decoding said composite complementary code simultaneously thereby identifying lower priority elements for removal from said bus; means coupled to said decoding means for removing each element's arbitration code from said common bus when said element has a lower priority arbitration code relative to another element supplying an arbitration code to said bus; and means for performing composite complementary code generation and decoding sequences until only a highest priority element of said plurality of elements remains on said bus and uses said bus for information transfer.

Claim 21

In combination: a plurality of elements interconnected by an asychronous common bus; means for generating a request in each of said elements to occupy said common bus; means coupled to said common bus in each of said elements for providing an element arbitration code for each of said elements; said common bus comprising means for performing a logical-OR of each bit of said element arbitration code on said bus for each of said elements forming a composite complementary code; means coupled to said common bus in each of said elements for decoding said composite complementary code simultaneously thereby identifying lower priority elements for removal from said bus; means coupled to said decoding means for removing each element's arbitration code from said common bus when said element has a lower priority arbitration code relative to another element supplying an arbitration code to said bus; and means for performing composite complementary code generation and decoding sequences until only a highest priority element of said plurality of elements remains on said bus and uses said bus for information transfer.

Claim 22

The combination as recited in claim 17 wherein: each of said elements includes a signal processor, a mass memory or an input-output controller.

Claim 23

The combination as recited in claim 17 wherein: said arbitration code comprises an address of said element.

Claim 24

The combination as recited in claim 17 wherein: each of said elements further comprises element address register means coupled to said decoding means and said common bus for changing an element's priority by changing the address of said element.

Claim 25

The combination as recited in claim 17 wherein: said logical-OR performing means for forming said composite complementary code comprises a wire-ORed bus.

Claim 28

The combination as recited in claim 17 wherein: said sequences performing means comprises a plurality of parallel AND gate means coupled to said common bus.

Claim 29

The combination as recited in claim 23 wherein: said sequences performing means further comprises a priority encoder means coupled to the output of said AND gate means.

Claim 30

The combination as recited in claim 24 wherein: said sequences performing means further comprises a conflict multiplexer means coupled to the output of said priority encoder means for generating a LOSE signal, said LOSE signal being coupled to an arbitration control means.

Claim 31

The combination as recited in claim 24 wherein: said priority encoder means comprises zero detect means for generating a WIN signal when only said highest priority element remains on said common bus.