Arbitration controller providing for access of a common resource by a duplex plurality of central processing units

Claim 1

An arbitration controller providing for equal priority sharing of duplicate copy resources by active ones of a plurality of duplicate pairs of CPUs, said arbitration controller comprising: first and second common buses, each bus including first and second portions; first and second switching means operated to provide alternate first and second selection signals; first and second arbitration groups, each of said groups including: first and second means for initialization, each providing a first signal; corresponding first and second pluralities of arbitration circuits, each plurality including a first, at least one successive and a last arbitration circuit; each of said means for initialization connected to at least one of said corresponding plurality of arbitration circuits; first and second pluralities of CPU buses each bus of each plurality connected between a particular CPU and said resources via a particular arbitration circuit on a one for one basis, each CPU bus including a control portion and an address/data portion; each of said buses of said first plurality connected to a particular one of said buses of said second plurality and each of said buses of said second plurality connected to a particular one of said buses of said first plurality; said first and second common buses, each common bus connected between said corresponding plurality of CPUs and a particular one of said duplicate copies of said resource via said corresponding arbitration circuits for the parallel transmission of information between said duplicate common resources and any said active one of said plurality of CPUs via said address/data portion of said corresponding CPU bus; first and second pluralities of circuit connections, each plurality including a circuit connection between each first arbitration circuit and each successive arbitration circuit, each of said last arbitration circuits connected to said first arbitration circuit of its respective plurality, thereby forming first and second completed ring connections, each of said ring connections propagating a respective one of said first signals synchronously; one arbitration circuit of each plurality simultaneously operated in response to its respective first signal and to a common bus request signal from said active CPU, each arbitration circuit producing a second signal for allowing said active CPU to access each of said duplicate copy resources simultaneously via said first and said second common buses respectively; each of said first signals propagating through each of said corresponding plurality of arbitration circuits to successively enable said active ones of said CPUs to access said duplicate copies of said resource; and said first switching means connected between said first and second portions of said first common bus and one copy of said resource, said second switching means connected between said first and second portions of said second common bus and said duplicate copy of said resource, whereby said first and second switching means each operates in response to said first selection signal to enable access to a copy of said duplicate copy resources from said arbitration circuits of said first portion of each said common bus and operates to disable said access from said arbitration circuits of said second portion of each common bus and alternately, each said switching means operates in response to said second selection signal to enable said access from said arbitration circuits of said second portion of each said common bus and to disable said access from said arbitration circuits of said first portion of each common bus.