US4359770A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bit buffer system
Assignee: Kokusai Denki Electric Inc
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Filing: 1980-03-24
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Granted: 1982-11-16
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Expires: 2000-03-24
Abstract
Abstract A bit buffer system wherein transmission data signals are sequentially stored in a shift register having a predetermined number of stages, the transmission data signal is taken out of a substantially central one of the predetermined number of stages at the time of initialization to be sent to a receiving unit, and the phase difference between the timing pulse controlling the period of the transmission data signal and the timing pulse controlling the operation of the receiving unit to select a specified stage of the shift register so as to take out the transmission data signal therefrom according to a detected phase difference. A specified code contained in the transmission coded data signal is detected to effect the initialization.
Inventors
- 👤 Kazuo Suzuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:42
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04J3/0635; H04J3/0685; H04L; H04L7/00; H04L7/0008; H04L7/0012; H04L7/02; H04L7/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
125 words
In a bit buffer system wherein transmission data signals are sequentially stored in a shift register with a predetermined number of stages, the transmission data signal is taken out from a substantially central one of the predetermined number of stages of said shift register upon initialization to be sent to a receiving unit, the phase difference between the timing pulse controlling the period of said transmission data signal and the timing pulse controlling the operation of said receiving unit is detected to select a specified stage of said register so as to take out said transmission data signal therefrom according to a detected phase difference, the improvement which comprises means detecting a specified code contained in said transmission data signal for carrying out said initialization.
Claim 2
Dependent Claim
125 words
In a bit buffer system wherein transmission data signals are sequentially stored in a shift register with a predetermined number of stages, the transmission data signal is taken out from a substantially central one of the predetermined number of stages of said shift register upon initialization to be sent to a receiving unit, the phase difference between the timing pulse controlling the period of said transmission data signal and the timing pulse controlling the operation of said receiving unit is detected to select a specified stage of said register so as to take out said transmission data signal therefrom according to a detected phase difference, the improvement which comprises means detecting a specified code contained in said transmission data signal for carrying out said initialization.
Claim 3
Dependent Claim
20 words
A bit buffer system as recited in claim 1 wherein the specified code comprises two or more successive synchronizing bits.
Claim 4
Dependent Claim
23 words
A bit buffer system as recited in claim 1 wherein the specified code comprises a mark code with successive 8 or more bits.
Claim 5
Dependent Claim
27 words
A bit buffer system as recited in claim 1 wherein the specified code comprises a condition where a space for one bit is included every 8 bits.
Claim 6
Dependent Claim
30 words
A bit buffer system as recited in claim 1 wherein the specified code comprises a condition representative of succession of two or more flag codes in HDLC transmission control procedure.
Claim 7
Dependent Claim
139 words
In a bit buffer system wherein transmission data signals are sequentially stored in a shift register with a predetermined number of stages, the transmission data signal is taken out from a substantially central one of the predetermined number of stages of said shift register upon initialization to be sent to a receiving unit, the phase difference between the timing pulse controlling the period of said transmission data signal and the timing pulse controlling the operation of said receiving unit is detected to select a specified stage of said register so as to take out said transmission data signal therefrom according to a detected phase difference, the improvement which comprises means for carrying out said initialization when a specified code contained in said transmission data signal is taken out of said shift register following the detection of the specified code.
Claim 8
Dependent Claim
139 words
In a bit buffer system wherein transmission data signals are sequentially stored in a shift register with a predetermined number of stages, the transmission data signal is taken out from a substantially central one of the predetermined number of stages of said shift register upon initialization to be sent to a receiving unit, the phase difference between the timing pulse controlling the period of said transmission data signal and the timing pulse controlling the operation of said receiving unit is detected to select a specified stage of said register so as to take out said transmission data signal therefrom according to a detected phase difference, the improvement which comprises means for carrying out said initialization when a specified code contained in said transmission data signal is taken out of said shift register following the detection of the specified code.
Claim 9
Dependent Claim
20 words
A bit buffer system as recited in claim 6 wherein the specified code comprises two or more successive synchronizing bits.
Claim 10
Dependent Claim
23 words
A bit buffer system as recited in claim 6 wherein the specified code comprises a mark code with successive 8 or more bits.
Claim 11
Dependent Claim
27 words
A bit buffer system as recited in claim 6 wherein the specified code comprises a condition where a space for one bit is included every 8 bits.
Claim 12
Dependent Claim
31 words
A bit buffer system as recited in claim 6 wherein the specified code comprises a condition representative of succession of two or more flag codes used in HDLC transmission control procedure.
References Cited (Backward Citations)
US3908084A
Cited
US4045618A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-11-15 | 1986-05-17 | 1986-11-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-11-15 | 1990-05-17 | 1990-11-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-11-15 | 1994-05-17 | 1994-11-16 | $7700.00 | Window Closed / Lapsed |