Method of producing low-resistance diffused regions in IC MOS semiconductor circuits in silicon-gate technology metal silicide layer formation

Claim 1

A method of producing relatively low-resistance diffused regions useful as current-supply paths in integrated MOS semiconductor circuits in silicon-gate technology wherein sheet resistance of such regions is reduced by formation of a metal silicide layer comprising, in combination, the sequential steps: (a) depositing a doped polysilicon layer of a given conductivity type on a monocrystalline silicon substrate of a conductivity type opposite to that of said given conductivity type; (b) depositing a layer of a metal which forms a silicide onto said polysilicon layer and converting a zone of such polycrystalline layer which lies relatively close to its surface into a metal silicide layer; (c) depositing a silicon dioxide layer onto the entire structure surface; (d) structuring the resultant SiO 2 -metal silicide-polycrystalline silicon triple layer in such a manner that regions of said monocrystalline substrate which are to form the low-resistance diffused regions remain covered; (e) producing a gate oxide via thermal oxidation and substantially simultaneously generating said low-resistance diffused regions in said monocrystalline substrate; (f) etching contact holes to said diffused regions of said monocrystalline substrate; (g) depositing a layer of undoped polysilicon on the entire structure surface; (h) locally oxidizing said undoped polysilicon layer via a nitride mask which covers gate regions and contact holes to said low-resistivity diffused regions; (i) doping said undoped polysilicon layer with a dopant of said given conductivity type; and (j) generating metal paths for completion of said circuit.

Claim 2

A method of producing relatively low-resistance diffused regions useful as current-supply paths in integrated MOS semiconductor circuits in silicon-gate technology wherein sheet resistance of such regions is reduced by formation of a metal silicide layer comprising, in combination, the sequential steps: (a) depositing a doped polysilicon layer of a given conductivity type on a monocrystalline silicon substrate of a conductivity type opposite to that of said given conductivity type; (b) depositing a layer of a metal which forms a silicide onto said polysilicon layer and converting a zone of such polycrystalline layer which lies relatively close to its surface into a metal silicide layer; (c) depositing a silicon dioxide layer onto the entire structure surface; (d) structuring the resultant SiO 2 -metal silicide-polycrystalline silicon triple layer in such a manner that regions of said monocrystalline substrate which are to form the low-resistance diffused regions remain covered; (e) producing a gate oxide via thermal oxidation and substantially simultaneously generating said low-resistance diffused regions in said monocrystalline substrate; (f) etching contact holes to said diffused regions of said monocrystalline substrate; (g) depositing a layer of undoped polysilicon on the entire structure surface; (h) locally oxidizing said undoped polysilicon layer via a nitride mask which covers gate regions and contact holes to said low-resistivity diffused regions; (i) doping said undoped polysilicon layer with a dopant of said given conductivity type; and (j) generating metal paths for completion of said circuit.