US4338599A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for alpha-numeric/graphic display
Assignee: Samsung Electronics Co Ltd
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Filing: 1980-04-18
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Granted: 1982-07-06
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Expires: 2000-04-18
Abstract
Abstract The computer system of this invention has, as the heart of the system, a simple processing unit for providing most data processing by the computer system under control of a read-only memory which contains only instructions and other data for the CPU. The system also includes a random access memory, a keyboard, a video terminal, and a port device in the form of a tape recorder/player. A master clock initiates timing used throughout the system. A multi-line data bus interconnects the CPU and the different memories of the system including the keyboard and the video RAM. Bi-directional communication is possible on the data bus. The addressing of these different memories is by way of an address bus from the CPU, which is a uni-directional bus. Data to be operated upon is basically stored in the random access memory. The keyboard is used for inputting data to the CPU and the video terminal is used for displaying data. Features of the present invention include a special reset scheme for the CPU, a multiplexing scheme for addressing the RAM, techniques for simply altering the control to provide capabilities of different capacity memories, alternate display of characters to provide, for example, either a 32-character line or a 64-character line, an improved keyboard selection scheme, and improved video processing means.
Inventors
- 👤 Steven Leininger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:16
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/22; G09G5/222
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
587 words
A system for generating and displaying characters on a video display means, comprising; video memory means for storing codes a portion of each which is representative of the character that is to be displayed represented as a character code and a portion of which is representative of character type as to being one of alpha-numeric and graphic type identified as a type code, a first data latch, means coupling the character code from the video memory means to the first data latch, timing means including means for generating timing control signals including a latch signal, a blanking signal, line address signals and a shift signal, means coupling the latch signal to the first data latch for controlling the latching of the character codes from the video memory means to the first data latch, a second data latch connected to the timing means and video memory means for storing control signals including the blanking signal, line address signal and type code, a character generator having input character code lines, input address lines and output dot lines, means coupling the character code from the first data latch to the input character code lines of the character generator, means coupling the line address signal to the input address lines of the character generator, a first shift register having input data lines, an output line, a shift line and a control line, means coupling the output dot lines from the character generator to the input data lines of the first shift register, means for providing a composite video signal, means coupling the first shift register output line to the means for providing a composite video signal, a graphic generator having input character code lines, input address lines and output dot lines, means coupling the character code from the first data latch to the input character code lines of the graphic generator, means coupling the line address signals to the input address lines of the graphic generator, a second shift register having input data lines, an output line, a shift line and a control line, means coupling the output dot lines from the graphic generator to the input data lines of the second shift register, means coupling the second shift register output line to the means for providing a composite video signal, first gate means having a plurality of input lines and an output line which couples to the control line of the first shift register for controlling the inputting of data into the first shift register, second gate means having a plurality of input lines and an output line which couples to the control line of the second shift register for controlling the inputting of data into the second shift register, means for coupling said shift signal to the shift line of said first and second shift registers, means applying a clock signal in common to an input line of both first and second gate means, means coupling the blanking signal from said second data latch in common to another input line of both first and second gate means, said second data latch including bistable means responsive to said type code for establishing mutually opposite first and second select signals, means coupling the first select signal to another input of only the first gate means to enable clocking of the first shift register when the type code indicates alpha-numeric display, and means coupling the second select signal to another input of only the second gate means to enable clocking of the second shift register when the type code indicates graphic display.
Claim 2
Independent Claim
587 words
A system for generating and displaying characters on a video display means, comprising; video memory means for storing codes a portion of each which is representative of the character that is to be displayed represented as a character code and a portion of which is representative of character type as to being one of alpha-numeric and graphic type identified as a type code, a first data latch, means coupling the character code from the video memory means to the first data latch, timing means including means for generating timing control signals including a latch signal, a blanking signal, line address signals and a shift signal, means coupling the latch signal to the first data latch for controlling the latching of the character codes from the video memory means to the first data latch, a second data latch connected to the timing means and video memory means for storing control signals including the blanking signal, line address signal and type code, a character generator having input character code lines, input address lines and output dot lines, means coupling the character code from the first data latch to the input character code lines of the character generator, means coupling the line address signal to the input address lines of the character generator, a first shift register having input data lines, an output line, a shift line and a control line, means coupling the output dot lines from the character generator to the input data lines of the first shift register, means for providing a composite video signal, means coupling the first shift register output line to the means for providing a composite video signal, a graphic generator having input character code lines, input address lines and output dot lines, means coupling the character code from the first data latch to the input character code lines of the graphic generator, means coupling the line address signals to the input address lines of the graphic generator, a second shift register having input data lines, an output line, a shift line and a control line, means coupling the output dot lines from the graphic generator to the input data lines of the second shift register, means coupling the second shift register output line to the means for providing a composite video signal, first gate means having a plurality of input lines and an output line which couples to the control line of the first shift register for controlling the inputting of data into the first shift register, second gate means having a plurality of input lines and an output line which couples to the control line of the second shift register for controlling the inputting of data into the second shift register, means for coupling said shift signal to the shift line of said first and second shift registers, means applying a clock signal in common to an input line of both first and second gate means, means coupling the blanking signal from said second data latch in common to another input line of both first and second gate means, said second data latch including bistable means responsive to said type code for establishing mutually opposite first and second select signals, means coupling the first select signal to another input of only the first gate means to enable clocking of the first shift register when the type code indicates alpha-numeric display, and means coupling the second select signal to another input of only the second gate means to enable clocking of the second shift register when the type code indicates graphic display.
Claim 3
Dependent Claim
41 words
A system as set forth in claim 1 wherein said second data latch includes a plurality of bistable means, one for storing the blanking signal, one for storing an address bit and one for storing one bit of the character code.
Claim 4
Dependent Claim
19 words
A system as set forth in claim 2 including means coupling the address bit to the first gate means.
Claim 5
Dependent Claim
37 words
A system as set forth in claim 2 including means for coupling the said one bit of the character code from the second data latch to one of the input character code lines of the character generator.
Claim 6
Dependent Claim
20 words
A system as set forth in claim 1 wherein said first and second gate means are both AND type gates.
Claim 7
Dependent Claim
18 words
A system as set forth in claim 1 wherein the clock signal is derived from the latch signal.
Claim 8
Dependent Claim
18 words
A system as set forth in claim 1 wherein the graphic generator comprises a multiple lines-to-single line multiplexer.
Claim 9
Dependent Claim
21 words
A system as set forth in claim 1 wherein the address signals include line address signals L1, L2, L4 and L8.
Claim 10
Dependent Claim
35 words
A system as set forth in claim 8 wherein the line address signals L1, L2 and L4 couple to the character generator and the line address signals L4 and L8 couple to the graphic generator.
Claim 11
Dependent Claim
41 words
A system as set forth in claim 8 wherein two line address signals are coupled to the graphic generator to define one of the upper most pair of cells, the middle pair of cells, and the lower most pair of cells.
Claim 12
Independent Claim
551 words
A system for generating and displaying characters on a video display means, comprising; video memory means for storing codes, a portion each of which is representative of the character that is to be displayed, represented as a character and a portion of which is representative of character type as to being one of alpha-numeric and graphic type identified as a type code, a data latch, means coupling the character code from the video memory means to the data latch, timing means including means for generating timing control signals, including clock, address, and shift signals, means coupling the clock signal to the data latch for controlling the latching of the character codes from the video memory means to the data latch, bistable means responsive to said type code for establishing mutually opposite first and second select signals, a character generator having input character code lines, input address lines, and output dot lines, means coupling the character code from the data latch to the input character code lines of the character generator, means coupling the address signals to the input address lines of the character generator, a first shift register having input data lines, an output line, a control line, and a shift line, means coupling the output dot lines from the character generator to the input data lines of the first shift register, means for providing a composite video signal, means coupling the first shift register output line to the means for providing a composite video signal, a graphic generator having input character code lines, input address lines, and output dot lines, means coupling the character code from the data latch to the input character code lines of the graphic generator, means coupling the address signals to the input address lines of the graphic generator, a second shift register having input data lines, an output line and a shift line, a control line, means coupling the output dot lines from the graphic generator to the input data lines of the second shift register, means coupling the second shift register output line to the means for providing a composite video signal, first AND gate means having a plurality of input lines and an output line which couples to the control line of the first shift register for controlling the clocking of data into said first shift register, second AND gate means having a plurality of input lines and an output line which couples to the control line of the second shift register for controlling the clocking of data into said second shift register, means for coupling said shift signal to the shift line of said first and second shift registers, means applying the clock signal in common to an input line of both first and second AND gate means, means coupling the first select signal to another input of the first AND gate means to enable clocking of the first shift register when the type code indicates alpha-numeric display, and means coupling the second select signal to another input of the second AND gate means to enable clocking of the second shift register when the type code indicates graphic display, said first and second AND gate means enabling data transfer to said respective first and second shift registers under the condition of all inputs to said gate means being in a predetermined state.
Claim 13
Independent Claim
551 words
A system for generating and displaying characters on a video display means, comprising; video memory means for storing codes, a portion each of which is representative of the character that is to be displayed, represented as a character and a portion of which is representative of character type as to being one of alpha-numeric and graphic type identified as a type code, a data latch, means coupling the character code from the video memory means to the data latch, timing means including means for generating timing control signals, including clock, address, and shift signals, means coupling the clock signal to the data latch for controlling the latching of the character codes from the video memory means to the data latch, bistable means responsive to said type code for establishing mutually opposite first and second select signals, a character generator having input character code lines, input address lines, and output dot lines, means coupling the character code from the data latch to the input character code lines of the character generator, means coupling the address signals to the input address lines of the character generator, a first shift register having input data lines, an output line, a control line, and a shift line, means coupling the output dot lines from the character generator to the input data lines of the first shift register, means for providing a composite video signal, means coupling the first shift register output line to the means for providing a composite video signal, a graphic generator having input character code lines, input address lines, and output dot lines, means coupling the character code from the data latch to the input character code lines of the graphic generator, means coupling the address signals to the input address lines of the graphic generator, a second shift register having input data lines, an output line and a shift line, a control line, means coupling the output dot lines from the graphic generator to the input data lines of the second shift register, means coupling the second shift register output line to the means for providing a composite video signal, first AND gate means having a plurality of input lines and an output line which couples to the control line of the first shift register for controlling the clocking of data into said first shift register, second AND gate means having a plurality of input lines and an output line which couples to the control line of the second shift register for controlling the clocking of data into said second shift register, means for coupling said shift signal to the shift line of said first and second shift registers, means applying the clock signal in common to an input line of both first and second AND gate means, means coupling the first select signal to another input of the first AND gate means to enable clocking of the first shift register when the type code indicates alpha-numeric display, and means coupling the second select signal to another input of the second AND gate means to enable clocking of the second shift register when the type code indicates graphic display, said first and second AND gate means enabling data transfer to said respective first and second shift registers under the condition of all inputs to said gate means being in a predetermined state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-05 | 1986-01-04 | 1986-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-05 | 1990-01-04 | 1990-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-05 | 1994-01-04 | 1994-07-06 | $7700.00 | Window Closed / Lapsed |