US4314348A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Signal processing with random address data array and charge injection output
Assignee: Bantec Inc
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Filing: 1979-06-05
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Granted: 1982-02-02
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Expires: 1999-06-05
Abstract
Abstract The weighted product of two digital signals obtained with a digital weighted template with corresponding binary signal stored within a two-dimensional matrix. Data is loaded into a circuit in word serial and random access modes. The weighted signal product is obtained using a vertical charge injection technique with sensing of the substrate analog charge flow. The substrate charge collection output permits a true summation of processed analog signals to provide the desired weighted product.
Inventors
- 👤 William N. Carr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:19
CPC Classifications
G; G06; G06J; G06J1/00; G06V; G06V10/00; G06V10/70; G06V10/74; G06V10/75; G06V10/751; H; H04; H04N; H04N25/00
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
79 words
A system for processing first and second digital signals to provide a weighted output, comprising; a first two-dimensional matrix register with serial addressed data input, said data input being said first digital signal, a second two-dimensional matrix register capable of serial or random address data input, said data input being said second digital signal, and a third register for receiving said first and second digital signals and providing said weighted output when said first and second digital signals match.
Claim 2
Independent Claim
79 words
A system for processing first and second digital signals to provide a weighted output, comprising; a first two-dimensional matrix register with serial addressed data input, said data input being said first digital signal, a second two-dimensional matrix register capable of serial or random address data input, said data input being said second digital signal, and a third register for receiving said first and second digital signals and providing said weighted output when said first and second digital signals match.
Claim 3
Dependent Claim
42 words
The system according to claim 1 wherein the first and second registers have a plurality of stages and each stage of the first register has a single bit cell and each stage of the second register has a plurality of bit cells.
Claim 4
Dependent Claim
20 words
The system according to claim 2 wherein each cell in said first register has bidirectional shift and static hold functions.
Claim 5
Dependent Claim
25 words
The system according to claim 2 wherein each cell in said second register includes means for being randomly addressed and means for statically retaining data.
Claim 6
Dependent Claim
21 words
The system according to claim 2 where at least two or more the plurality of bit cells include a weighting factor.
Claim 7
Dependent Claim
34 words
The system according to claim 1 wherein the output from each stage of the third register provides an incremental charge component which is summed throughout the entire third register for a single analog output.
Claim 8
Dependent Claim
45 words
The system according to claim 6 wherein the third register is an array of charged coupled devices formed on a common substrate with a summing node within each stage, and the charge at each stage is injected into the substrate to provide the system output.
Claim 9
Independent Claim
60 words
A system for processing digital signals and producing a weighted output therefrom comprising; first means for shifting a serial digital signal therethrough, a second means for storing a multibit digital signal and third means for receiving the serial digital signal and the multibit digital signal and forming a product of the two signals and outputing the product in analog form.
Claim 10
Independent Claim
60 words
A system for processing digital signals and producing a weighted output therefrom comprising; first means for shifting a serial digital signal therethrough, a second means for storing a multibit digital signal and third means for receiving the serial digital signal and the multibit digital signal and forming a product of the two signals and outputing the product in analog form.
Claim 11
Dependent Claim
16 words
The system according to claim 8 wherein some bits of the multibit digital signal are weighted.
Claim 12
Dependent Claim
18 words
The system according to claim 8 wherein the second means for storing multibit digital signals is randomly adressable.
Claim 13
Dependent Claim
32 words
The system according to claim 8 wherein said first and second means are in the form of two dimensional matrices having J rows and K columns and the two matrices are cross-coupled.
Claim 14
Dependent Claim
22 words
The system according to claim 8 wherein the input to said second means may be either sequential words or randomly addressed words.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-02-01 | 1985-08-03 | 1986-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-02-01 | 1989-08-03 | 1990-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-02-01 | 1993-08-03 | 1994-02-02 | $7700.00 | Window Closed / Lapsed |