US4298936A
Expired / Lapsed
US
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Array Processor
Assignee: Analogic Corp
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Filing: 1979-11-15
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Granted: 1981-11-03
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Expires: 1999-11-15
Abstract
Abstract In an Array Processor, a buffering unit including a FIFO buffer and serial-to-parallel converter, is interposed between a control processor and the remainder of the Array Processing circuitry so as to permit the utilization of a vertical instruction set for generating addresses and function numbers which are then serially coupled from the control processor to the buffering unit.
Inventors
- 👤 Gerald N. Shapiro
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:59
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/3017; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/38; G06F9/3877; G06F9/3879; G06F9/3885; G06F9/3887; G06F9/38873
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
55 words
An Array Processor comprising in combination: a controller having serially generated words as an output therefrom; a buffering unit including a FIFO buffer and a serial-to-parallel converter coupled thereto: means for coupling said serially generated words to said buffering unit; and, a pipelined arithmetic unit and memory coupled to said buffering unit and controlled thereby.
Claim 2
Dependent Claim
55 words
An Array Processor comprising in combination: a controller having serially generated words as an output therefrom; a buffering unit including a FIFO buffer and a serial-to-parallel converter coupled thereto: means for coupling said serially generated words to said buffering unit; and, a pipelined arithmetic unit and memory coupled to said buffering unit and controlled thereby.
Claim 3
Dependent Claim
73 words
An Array Processor comprising in combination: a controller; means for inputting a serial instruction set into said controller such that the output of said controller includes serially generated words; a buffering unit coupled to said controller, said buffering unit including an FIFO buffer and a serial-to-parallel converter coupled thereto for converting the serially generated words into parallel fields; and, a pipelined arithmetic unit and memory coupled to and controlled by the parallel fields.
Claim 4
Dependent Claim
73 words
An Array Processor comprising in combination: a controller; means for inputting a serial instruction set into said controller such that the output of said controller includes serially generated words; a buffering unit coupled to said controller, said buffering unit including an FIFO buffer and a serial-to-parallel converter coupled thereto for converting the serially generated words into parallel fields; and, a pipelined arithmetic unit and memory coupled to and controlled by the parallel fields.
Claim 5
Independent Claim
76 words
A method of facilitating the programming of an Array Processor having a controller and a pipelined arithmetic unit/memory section comprising: interposing a buffering unit between the controller and the pipelined arithmetic unit/memory section for the control of the arithmetic unit/memory section, the buffering unit providing parallel fields corresponding to a serially developed set of words; and, providing the controller with a vertical instruction set such that the controller generates a corresponding serially developed set of words.
Claim 6
Independent Claim
76 words
A method of facilitating the programming of an Array Processor having a controller and a pipelined arithmetic unit/memory section comprising: interposing a buffering unit between the controller and the pipelined arithmetic unit/memory section for the control of the arithmetic unit/memory section, the buffering unit providing parallel fields corresponding to a serially developed set of words; and, providing the controller with a vertical instruction set such that the controller generates a corresponding serially developed set of words.
Claim 7
Dependent Claim
15 words
The method of claim 3 wherein said parallel fields are outputted at a fixed rate.
Claim 8
Dependent Claim
33 words
The method of claim 4 wherein the rate at which the vertical instruction set is processed by the controller is higher than the fixed rate of the parallel output from the buffering unit.
Claim 9
Independent Claim
46 words
A method of eliminating waste in the control of an Array Processor, comprising: providing the Array Processor with a vertical instruction set and means for converting the vertical instruction set into a set of parallel fields read out to the pipelined arithmetic and memory sections thereof.
Claim 10
Independent Claim
46 words
A method of eliminating waste in the control of an Array Processor, comprising: providing the Array Processor with a vertical instruction set and means for converting the vertical instruction set into a set of parallel fields read out to the pipelined arithmetic and memory sections thereof.
Claim 11
Dependent Claim
16 words
The method of claim 6 wherein said parallel fields are read out at a fixed rate.
Claim 12
Dependent Claim
23 words
The method of claim 7 wherein the rate at which the vertical instruction set is provided is higher than the fixed output rate.
Claim 13
Dependent Claim
65 words
An Array Processor comprising in combination: a controller having serially generated words as an output therefrom; a buffering unit including means for converting said serially generated words into a parallel format; means for coupling said serially generated words to said buffering unit; and, a pipelined arithmetic unit and memory coupled to said buffering unit and controlled by the parallel formatted words from said buffering unit.
Claim 14
Dependent Claim
65 words
An Array Processor comprising in combination: a controller having serially generated words as an output therefrom; a buffering unit including means for converting said serially generated words into a parallel format; means for coupling said serially generated words to said buffering unit; and, a pipelined arithmetic unit and memory coupled to said buffering unit and controlled by the parallel formatted words from said buffering unit.
Claim 15
Dependent Claim
77 words
Apparatus for facilitating the programming of an Array Processor having a controller and a pipelined arithmetic unit/memory section comprising: a buffering unit interposed between the controller and the pipelined arithmetic unit/memory section for the control of the arithmetic unit/memory section, the buffering unit providing parallel fields corresponding to a serially developed set of words; and, means for providing the controller with a vertical instruction set such that the controller generates a corresponding serially developed set of words.
Claim 16
Dependent Claim
77 words
Apparatus for facilitating the programming of an Array Processor having a controller and a pipelined arithmetic unit/memory section comprising: a buffering unit interposed between the controller and the pipelined arithmetic unit/memory section for the control of the arithmetic unit/memory section, the buffering unit providing parallel fields corresponding to a serially developed set of words; and, means for providing the controller with a vertical instruction set such that the controller generates a corresponding serially developed set of words.
Claim 17
Dependent Claim
20 words
The apparatus of claim 10 wherein said buffering unit includes means for outputting said parallel fields at a fixed rate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-11-02 | 1985-05-04 | 1985-11-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-11-02 | 1989-05-04 | 1989-11-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-11-02 | 1993-05-04 | 1993-11-03 | $7700.00 | Window Closed / Lapsed |