US4295264A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making integrated circuit MOS capacitor using implanted region to change threshold
Assignee: Texas Instruments Inc
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Filing: 1976-11-15
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Granted: 1981-10-20
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Expires: 1996-11-15
Abstract
Abstract An MOS capacitor for N-channel silicon gate integrated circuits employs a polycrystalline silicon layer as one plate, and a silicon oxide dielectric. The lower plate consists of a region which is implanted by an ion beam to produce a depleted region. This device has a constant capacitance regardless of gate voltage in normal operating logic levels.
Inventors
- 👤 Gerald D. Rogers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:00
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/21; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10P30/202; H10P30/204
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
184 words
A method of making an MOS integrated circuit device having a capacitor comprising the steps of: a. providing a body of silicon having an area on a major face thereof for a capacitor device; b. implanting a shallow surface-adjacent part of said area with conductivity-determining impurity to create a capacitor region in the surface of the silicon to function as the lower plate of the capacitor, the capacitor region being implanted to an impurity concentration selected to exhibit a threshold of the capacitor substantially different from that of the silicon not implanted whereby such region has a threshold less than zero volts; c. providing a coating of silicon oxide on said area as the capacitor dielectric; d. applying a layer of polycrystalline silicon over said coating of silicon oxide to provide the upper plate of the capacitor; e. and diffusing impurity material into the major face near and on one side of said area to a depth much greater than that of said shallow surface-adjacent implanted part to provide electrical connections to the capacitor region, using said coating of silicon oxide as a mask.
Claim 2
Independent Claim
184 words
A method of making an MOS integrated circuit device having a capacitor comprising the steps of: a. providing a body of silicon having an area on a major face thereof for a capacitor device; b. implanting a shallow surface-adjacent part of said area with conductivity-determining impurity to create a capacitor region in the surface of the silicon to function as the lower plate of the capacitor, the capacitor region being implanted to an impurity concentration selected to exhibit a threshold of the capacitor substantially different from that of the silicon not implanted whereby such region has a threshold less than zero volts; c. providing a coating of silicon oxide on said area as the capacitor dielectric; d. applying a layer of polycrystalline silicon over said coating of silicon oxide to provide the upper plate of the capacitor; e. and diffusing impurity material into the major face near and on one side of said area to a depth much greater than that of said shallow surface-adjacent implanted part to provide electrical connections to the capacitor region, using said coating of silicon oxide as a mask.
Claim 3
Dependent Claim
12 words
A method according to claim 1 wherein the body is predominantly P-type.
Claim 4
Dependent Claim
17 words
A method according to claim 2 wherein the impurity material diffused into the major face is N-type.
Claim 5
Dependent Claim
12 words
A method according to claim 3 wherein the conductivity-determining impurity is phosphorus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-19 | 1985-04-20 | 1985-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-19 | 1989-04-20 | 1989-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-19 | 1993-04-20 | 1993-10-20 | $7700.00 | Window Closed / Lapsed |