US4291371A
Expired / Lapsed
US
⏱️ 0.0 years remaining
I/O Request interrupt mechanism
Assignee: Bull HN Information Systems Inc
•
Filing: 1979-01-02
•
Granted: 1981-09-22
•
Expires: 1999-01-02
Abstract
Abstract Apparatus for intercepting a channel program that is operative with a particular input/output device when an input/output device of higher priority requests service. The channel program is intercepted at a time when the processor is required to process a minimum of information. This enables the processor to be readily operative with the original input/output device.
Inventors
- 👤 Thomas O. Holtey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/26
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
220 words
In a computer system having a microprocessor (μP) for executing channel routines and subroutines, a U-bus coupled to said microprocessor, a main memory, an M-bus coupled to said main memory, a bus-driver coupled to said M-bus and said U-bus for enabling and disabling information flow between said M-bus and said U-bus, an instruction register (I-register) coupled to said U-bus for storing instructions which initiate or obviate interrupt operation and a plurality of communication devices also coupled to said U-bus for generating interrupt requests, an interrupt apparatus for processing interrupt requests, said interrupt apparatus comprising: (a) first means for generating signals forming a predetermined address at the end of every channel subroutine; (b) second means coupled to said μP for interrupting said μP, said second means being enabled by said predetermined address signals; (c) third means for deriving signals forming the next sequential address from said predetermined address, said next sequential address signals used for enabling said I-register to transfer said instructions to said U-bus and for disabling said bus-driver, whereby a normal memory read data path including said M-bus and said bus-driver is disabled; and (d) fourth means coupled to said I-register and to said plurality of communication devices for intercepting an interrupt request from one of said plurality of communication devices and for forming said instructions in said I-register.
Claim 2
Dependent Claim
220 words
In a computer system having a microprocessor (μP) for executing channel routines and subroutines, a U-bus coupled to said microprocessor, a main memory, an M-bus coupled to said main memory, a bus-driver coupled to said M-bus and said U-bus for enabling and disabling information flow between said M-bus and said U-bus, an instruction register (I-register) coupled to said U-bus for storing instructions which initiate or obviate interrupt operation and a plurality of communication devices also coupled to said U-bus for generating interrupt requests, an interrupt apparatus for processing interrupt requests, said interrupt apparatus comprising: (a) first means for generating signals forming a predetermined address at the end of every channel subroutine; (b) second means coupled to said μP for interrupting said μP, said second means being enabled by said predetermined address signals; (c) third means for deriving signals forming the next sequential address from said predetermined address, said next sequential address signals used for enabling said I-register to transfer said instructions to said U-bus and for disabling said bus-driver, whereby a normal memory read data path including said M-bus and said bus-driver is disabled; and (d) fourth means coupled to said I-register and to said plurality of communication devices for intercepting an interrupt request from one of said plurality of communication devices and for forming said instructions in said I-register.
Claim 3
Dependent Claim
21 words
The apparatus as recited in claim 1 wherein the fourth means includes a PROM connected to said plurality of communications devices.
Claim 4
Dependent Claim
15 words
The apparatus as recited in claim 2 wherein said bus-driver comprises a bidirectional tri-state circuit.
Claim 5
Dependent Claim
194 words
In a computer system having a data processing unit for executing channel routines and an instruction register for providing instruction data to said unit, and a memory containing control instructions, a method of intercepting and processing interrupt requests comprising the steps of: receiving interrupt requests; utilizing said interrupt requests to address a PROM containing control data; determining interrupt priorities based on the control data contained in said PROM at the locations addressed during said step of utilizing; checking for the presence of interrupt requests only when a currently operating channel subroutine has been completed, whereupon said system is required to store a minimum amount of information to enable processing of an interrupt request; suspending execution of the current channel routine during said checking operation and processing any interrupt requests detected during said checking operation; and continuing execution of said channel routine when no interrupts are detected during said checking operation; generating and entering a first instruction data sequence in said instruction register if an interrupt request is present; generating and entering a second instruction data sequence if no interrupt request is present; and transmitting the instruction in said instruction register to said processing unit.
Claim 6
Dependent Claim
194 words
In a computer system having a data processing unit for executing channel routines and an instruction register for providing instruction data to said unit, and a memory containing control instructions, a method of intercepting and processing interrupt requests comprising the steps of: receiving interrupt requests; utilizing said interrupt requests to address a PROM containing control data; determining interrupt priorities based on the control data contained in said PROM at the locations addressed during said step of utilizing; checking for the presence of interrupt requests only when a currently operating channel subroutine has been completed, whereupon said system is required to store a minimum amount of information to enable processing of an interrupt request; suspending execution of the current channel routine during said checking operation and processing any interrupt requests detected during said checking operation; and continuing execution of said channel routine when no interrupts are detected during said checking operation; generating and entering a first instruction data sequence in said instruction register if an interrupt request is present; generating and entering a second instruction data sequence if no interrupt request is present; and transmitting the instruction in said instruction register to said processing unit.
Claim 7
Dependent Claim
22 words
The method of claim 4 wherein said step of suspending and processing includes the step of: executing said second instruction data sequence.
Claim 8
Dependent Claim
25 words
The method in claim 5 wherein said step of continuing execution of said channel routine includes the step of: executing said second instruction data sequence.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-09-21 | 1985-03-23 | 1985-09-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-09-21 | 1989-03-23 | 1989-09-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-09-21 | 1993-03-23 | 1993-09-22 | $7700.00 | Window Closed / Lapsed |