US4287570A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple bit read-only memory cell and its sense amplifier
Assignee: Intel Corp
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Filing: 1979-06-01
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Granted: 1981-09-01
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Expires: 1999-06-01
Abstract
Abstract The bit density of stored information in a read-only memory (ROM) can be substantially increased by increasing the number of bits which can be stored in each memory cell. This can be accomplished without increasing the size or complexity of the memory cell by having the read only memory capacity stored in each memory cell as one of a multiple number of discrete states achievable by the cell. In a semiconductor chip this can be accomplished by having the semiconductor element, such as a transistor, capable of assuming one of a multiple of parametric values or states. For example, as described herein, impedance or cell width of a semiconductor transistor can be varied to assume one of four different states. The state assigned to a selected memory cell is bracketed by the value of the outputs of a plurality of comparator circuits coupled thereto. The outputs of the comparator circuits are then analyzed by a logic circuit to provide the appropriate binary readout representative of the parametric state of the selected cell.
Inventors
- 👤 Moshe Stark
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:20
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/5692; G11C7/00; G11C7/06
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
288 words
A memory circuit comprising: characterizing source-to-drain width assuming a selected one of a discrete plurality of values; comparator means coupled to said circuit device for comparing said selected one value of said width of said transistor against at least one predetermined value; and logic means coupled to said comparator means for decoding the output of said comparator means into a number, said number having maximum magnitude equal to said discrete plurality of values of said width of said transistor, wherein said comparator means has a plurality of outputs one less in number than said discrete plurality of values of said transistor wherein each said output corresponds to a predetermined value, each said predetermined value being nested between two of said discrete plurality of values of said width of said transistor; and wherein said comparator means includes a differential amplifier to compare said selected one of said discrete plurality of values of said width of said transistor against said predetermined value wherein said sense amplifier is comprised of a biased reference inverter, a biased sense inverter, a reference voltage source, a sense voltage source coupled to said field effect transistor, and an output amplifier, said sense voltage and reference voltage sources being substantially identical in circuit design and coupled to said biased inverters, said sense inverter coupled to said sense voltage source and said reference inverter coupled to said reference voltage source, said sense and reference inverters being coupled to the inputs of said output amplifier whereby analog voltages are analyzed by said comparator means to reliably produce digital voltage levels independent and self-compensating for changes in temperature, voltage, dimension and process variations; whereby a memory circuit may be devised having more than two states for each memory cell.
Claim 2
Dependent Claim
288 words
A memory circuit comprising: characterizing source-to-drain width assuming a selected one of a discrete plurality of values; comparator means coupled to said circuit device for comparing said selected one value of said width of said transistor against at least one predetermined value; and logic means coupled to said comparator means for decoding the output of said comparator means into a number, said number having maximum magnitude equal to said discrete plurality of values of said width of said transistor, wherein said comparator means has a plurality of outputs one less in number than said discrete plurality of values of said transistor wherein each said output corresponds to a predetermined value, each said predetermined value being nested between two of said discrete plurality of values of said width of said transistor; and wherein said comparator means includes a differential amplifier to compare said selected one of said discrete plurality of values of said width of said transistor against said predetermined value wherein said sense amplifier is comprised of a biased reference inverter, a biased sense inverter, a reference voltage source, a sense voltage source coupled to said field effect transistor, and an output amplifier, said sense voltage and reference voltage sources being substantially identical in circuit design and coupled to said biased inverters, said sense inverter coupled to said sense voltage source and said reference inverter coupled to said reference voltage source, said sense and reference inverters being coupled to the inputs of said output amplifier whereby analog voltages are analyzed by said comparator means to reliably produce digital voltage levels independent and self-compensating for changes in temperature, voltage, dimension and process variations; whereby a memory circuit may be devised having more than two states for each memory cell.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-08-31 | 1985-03-02 | 1985-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-08-31 | 1989-03-02 | 1989-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-08-31 | 1993-03-02 | 1993-09-01 | $7700.00 | Window Closed / Lapsed |