Method of addressing and/or locating information on a record carrier

Claim 2

An improved method of addressing and locating information on a record carrier used in an information recording and playback system, the addresses being recorded in the form of digital pulse trains in the same track of said record carrier, wherein the improvement comprises: recording an address with a sub-audo frequency at recording and playback speed on said record carrier by recording consecutively at least two preamble pulses and a number of pulses and intervals, corresponding to the ones and zeros of the digitized address, and a number of post-amble pulses equal to the number of preamble pulses; entering said address into a first address memory; erasing simultaneously a previous address contained in said first address memory when entering said digitized address into said address memory; starting the record carrier transport; starting a pulse counter upon the first preamble pulse when an address passes a read head; advancing said counter one step upon each subsequent pulse; measuring the interval between the first two preamble pulses; storing predetermined values in a second memory; comparing said interval with values stored in said second memory, which values correspond to the minimum and maximum speed of said record carrier; and, storing the measured value if it lies between said minimum and maximum speed values in a third memory; measuring the interval between the two consecutive preamble pulses if the number of preamble pulses is greater than two, determining whether a code pulse appears in a time window near the end of the subsequent intervals which are equal to the mean of the preamble intervals if, within certain limits, the measured values are equal to the interval between the first and second preamble pulse; storing a binary value in a code memory, the value being a function of the appearance or non-appearance of a pulse in a time window; advancing the pulse counter one step after each interval until said pulse counter reaches a count which is equal to the sum of the total member of preamble, code and post-amble pulses; comparing the content of said code memory with the content of said address memory; stopping the record carrier transport if said contents correspond in anticipation of re-starting at playback speed; switching directly to playback speed; and moving said record carrier forward if the content of said code memory is smaller than that of said address memory; moving the record carrier in the reverse direction if the content of said code memory is greater than that of the address memory.

Claim 3

A method as claimed in claim 1, further comprising: inserting check bits between said code pulses, the beginning of the code pulse intervals being synchronized with these check bits; and ascertaining the presence of said check bits during searching.

Claim 4

A method as claimed in claim 1 or 2, further comprising: inserting a check bit at one of two adjoining fixed locations in the code bit row.

Claim 5

A method as claimed in claim 1, further comprising: rejecting the code as an address after the code has been read into the code memory if all code bits have the same value.

Claim 6

An improved apparatus for addressing and locating information on a record carrier provided with means for the insertion of addresses in the informaiton tracks on said record carrier, comprising: a first, address memory connected to a device for erasing the address memory and entering an address in digital form into said address memory; an address generator connected to said address memory, for generating an address corresponding to the address in said address memory with a sub-audio frequency at recording and playback speed, which address comprises at least two preamble pulses a number of pulses and intervals corresponding to the ones and zeros in said address memory, and a number of post-amble pulses equal to the number of preamble pulses; a circuit connected to said address generator output having a write head for recording said addresses; a read head connected to a pulse counter which upon the arrival of the first pre-amble pulse of an address is started and which is advanced one step by each subsequent pulse (and interval); a time measuring device also started by said first preamble pulse and which measures the interval between every two preamble pulses; a second memory which stores the intervals between the first two preamble pulses, corresponding to the minimum and maximum speed of the record carrier; a first comparator to which both the time measuring device and the second memory are connected; a third memory connected to the output of said first comparator at which a signal appears, if the interval measured by the time measuring device falls between the two values stored in said second memory; said third memory also connected to said time measuring device for the storage of the measured interval; a second comparator connected to said time measuring device being connected directly and, if the number of preamble pulses is greater than two, also connected to said third memory, for the comparison of the intervals between the first and second preamble pulses and the subsequent preamble pulses; means to determine the mean value of these intervals; a time window circuit which supplies a signal for a specific period of time around the end of each mean interval; a sampling circuit connected to said time window circuit which during the time window determines whether a pulse appears during an interval; a code memory connected to said sampling circuit, in which a code is stored; a first switching device; a third comparator, whose first inputs are connected to the outputs of said code memory and whose second inputs are connected to said address memory and whose first output, at which a signal appears if the content of the code memory corresponds to the content of said address memory; the stop switch of said record carrier connected to said third comparator; a switch connected to a second output of said third comparator, at which output a signal appears if the content of the code memory is smaller than that of the address memory for the forward transport of the record carrier; a switch for the reverse transport of the record carrier connected to a third output of the third comparator, at which output a signal appears if the content of the code memory is greater than the address memory.

Claim 7

An improved apparatus for addressing and locating information on a record carrier provided with means for the insertion of addresses in the informaiton tracks on said record carrier, comprising: a first, address memory connected to a device for erasing the address memory and entering an address in digital form into said address memory; an address generator connected to said address memory, for generating an address corresponding to the address in said address memory with a sub-audio frequency at recording and playback speed, which address comprises at least two preamble pulses a number of pulses and intervals corresponding to the ones and zeros in said address memory, and a number of post-amble pulses equal to the number of preamble pulses; a circuit connected to said address generator output having a write head for recording said addresses; a read head connected to a pulse counter which upon the arrival of the first pre-amble pulse of an address is started and which is advanced one step by each subsequent pulse (and interval); a time measuring device also started by said first preamble pulse and which measures the interval between every two preamble pulses; a second memory which stores the intervals between the first two preamble pulses, corresponding to the minimum and maximum speed of the record carrier; a first comparator to which both the time measuring device and the second memory are connected; a third memory connected to the output of said first comparator at which a signal appears, if the interval measured by the time measuring device falls between the two values stored in said second memory; said third memory also connected to said time measuring device for the storage of the measured interval; a second comparator connected to said time measuring device being connected directly and, if the number of preamble pulses is greater than two, also connected to said third memory, for the comparison of the intervals between the first and second preamble pulses and the subsequent preamble pulses; means to determine the mean value of these intervals; a time window circuit which supplies a signal for a specific period of time around the end of each mean interval; a sampling circuit connected to said time window circuit which during the time window determines whether a pulse appears during an interval; a code memory connected to said sampling circuit, in which a code is stored; a first switching device; a third comparator, whose first inputs are connected to the outputs of said code memory and whose second inputs are connected to said address memory and whose first output, at which a signal appears if the content of the code memory corresponds to the content of said address memory; the stop switch of said record carrier connected to said third comparator; a switch connected to a second output of said third comparator, at which output a signal appears if the content of the code memory is smaller than that of the address memory for the forward transport of the record carrier; a switch for the reverse transport of the record carrier connected to a third output of the third comparator, at which output a signal appears if the content of the code memory is greater than the address memory.

Claim 8

An apparatus as claimed in claim 5 further including a second switching device having a control input connected to the location of the code memory in which a check bit is stored and connected in series with the first switching device.

Claim 9

An apparatus as claimed in claim 5 or 6 wherein the adjoining locations in the code memory, which should contain one check bit in the code, are connected to the input of at least one, the output of the OR-circuit being connected to the control input of the second switching device.

Claim 10

An apparatus as claimed in claim 6 wherein the outputs of the code memory are each connected to an input of an AND-circuit, whose output leads to the control input of a third switching device, which is connected in series with the first switching device.

Claim 11

An aparatus as claimed in claim 5, wherein there is provided a programmable digital signal processing unit controlled by a program.