Special-purpose digital computer for statistical data processing

Claim 1

A special-purpose digital computer for statistical data processing, comprising: input data lines; output lines; a random-number generator, for producing a uniform pseudo-random number sequence, having an input and a multi-channel output; first and second stochastic data rounding units, for linear conversion of the code into its probability and for stochastic rounding of numbers, each having a first multi-channel input connected to respective input data lines, a second multi-channel input, an input, a multi-channel output, and an output; third and fourth stochastic data rounding units, for linear conversion of the code into its probability and for stochastic rounding of numbers, each having first and second multi-channel inputs, an input and an output; a shift register unit having a multi-channel input, an input, and a multi-channel output connected to said multi-channel input of said shift register unit; a first receiving register having a multi-channel input connected to said multi-channel output of said shift register, an input, and a multi-channel output connected to said first multi-channel input of said third stochastic data rounding unit; a second receiving register having a multi-channel input, an input, and a multi-channel output connected to said multi-channel input of said shift register unit and to said first multi-channel input of said fourth stochastic data rounding unit; a third receiving register having a multi-channel input connected to said multi-channel output of said shift register unit, an input, and a multi-channel output connected to said first multi-channel input of said first stochastic data rounding unit; a single-time step multiplier, for stochastic multiplication of numbers, having a first input connected to said output of said third stochastic data rounding unit, a second input connected to said output of said fourth stochastic data rounding unit, and an output; a senior address digit register having a multi-channel input, first and second inputs, and a multi-channel output; a junior address digit register having a multi-channel input, first and second inputs, a multi-channel output, and an output connected to said first input of said senior address digit register; a decoder having a multi-channel input connected to said multi-channel outputs of said senior address digit register and of said junior address digit register, an input, and a multi-channel output; a logical memory, for accumulating and storing data, adding numbers and summing unity increments of numbers, having a first multi-channel input connected to said multi-channel output of said decoder, a second multi-channel input, a third multi-channel input, a first input connected to said outputs of said third and fourth stochastic data rounding units and to said output of said multiplier, and a second input, an output connected to said first input of said junior address digit register, and a multi-channel output connected to said first multi-channel inputs of said logical memory and of said first and second stochastic data rounding units, to said multi-channel input of said first receiving register, and to said output lines; a read only memory, for storing harmonic functions, "correlation window" functions, logarithmic functions, correlation factors and microinstructions, having a first multi-channel input connected to said multi-channel output of said logical memory, a second multi-channel input, a first multi-channel output connected to said second multi-channel input of said logical memory, and a second multi-channel output; a quantization step counter, for determining the value of a quantization amplitude interval, having first and second multi-channel outputs respectively connected to said second multi-channel inputs of said first and second stochastic data rounding unit, and an input; a clock having a first multi-channel input connected to said second multi-channel output of said read only memory, a second multi-channel input connected to said multi-channel output of said random number generator, a first multi-channel output connected to said second multi-channel input of said read only memory, a second multi-channel output, and an output connected to said inputs of said random number generator, said first, second, third and fourth stochastic data rounding units, said shift register unit, said first, second and third receiving registers, and said decoder and to said second inputs of said senior address digit register, and said junior address digit register, and connected to said third multi-channel input of said logical memory; and a distributor, for distributing information depending on the operating modes of the special-purpose digital computer, having first and second multi-channel inputs respectively connected to said multi-channel outputs of said first and second stochastic data rounding units, a second multi-channel input connected to said second multi-channel output of said clock, a third multi-channel input connected to said multi-channel outputs of said senior address digit register and said junior address digit register, first and second inputs respectively connected to said outputs of said first and second stochastic data rounding units, a first multi-channel output connected to said second multi-channel inputs of said first, second, third and fourth stochastic data rounding units, a second multi-channel output connected to said multi-channel inputs of said senior address digit register and said junior address digit register, third and fourth multi-channel outputs respectively connected to said multi-channel inputs of said first and second receiving registers, a first output connected to said input of said quantization step counter, and a second output conneced to said second input of said logical memory.