System and method for accessing memory connected to different bus and requesting subsystem

Claim 2

In a data processing system including first and second busses each having a plurality of addressable ports, a system comprising in combination: (a) a memory subsystem connected to a first port of said second bus; (b) a subsystem connected to a second port of said first bus, said subsystem including i. a plurality of input/output means for transmitting a request message to said first bus; ii. means for inserting first identification information into said request message, representing a one of said input/output means from which said request message is transmitted; (c) means coupled to said first and second busses, respectively, for routing said request message from said first bus to said second bus and routing any memory response message produced in response to said request message by said memory subsystem from said second bus to said first bus, said routing means including i. means for receiving said request message from said first bus and determining if said request message requires a response from said memory subsystem; ii. means for temporarily storing said first identification information; iii. means responsive to said request message receiving means for modifying said request message to contain second identification information representing an addressable port on said second bus and the location of said stored first identification information in said means for temporarily storing; iv. means for transmitting said modified request message to said memory subsystem via said second bus.

Claim 3

The system of claim 1 further including means in said routing means for receiving said memory response message from said second bus and modifying said memory response message to contain said first identification information.

Claim 4

The system of claim 2 further including means in said routing means for transmitting said modified memory response message to said subsystem via said first bus.

Claim 5

The system of claim 3 further including means in said subsystem for routing said modified memory response message to the one of said input/output means identified by said first identification information.

Claim 6

The system of claim 1 wherein said routing means includes: (a) a first memory communications adaptor circuit coupled to a third port of said first bus, said third port being the same address code as said second port of said second bus; (b) a second memory communications adaptor circuit coupled to a fourth port of said second bus; and (c) cable means for coupling said first memory communications adaptor to said second memory communications adaptor.

Claim 7

The system of claim 5 wherein said request message receiving means includes decoding means in said second memory communications adaptor for decoding an op code of said request message to determine if said request message requires a response from said memory subsystem.

Claim 8

The system of claim 5 wherein said memory message modifying means includes a local bus adaptor in said memory subsystem.

Claim 9

The system of claim 5 wherein said first and second memory communications adaptors are substantially similar.

Claim 10

In a data processing system including first and second time-shared busses each having a plurality of addressable ports, a system comprising in combination: (a) a memory subsystem connected to a first port of said second bus; (b) a subsystem connected to a second port of said first bus, said subsystem including i. a plurality of input/output means for transmitting a request message to said first bus; ii. means for providing first identification information in said request message, said identifying information representing a one of said input/output means from which said request message is transmitted; (c) means coupled to said first and second busses, respectively, for routing said request message from said first bus to said second bus and routing any memory response message produced in response to said request message by said memory subsystem from said second bus to said first bus, said routing means including i. means for receiving said request message from said first bus and determining if said request message requires a response from said memory subsystem; ii. means responsive to said request message receiving means for removing said first identification information from said request message and temporarily storing said first identification information; iii. means for modifying said request message to contain second identification information representing an addressable port on said second bus and the location of said stored first identification information in said responsive means if said request message requires a response from said memory subsystem; iv. means for transmitting said modified request message to said memory subsystem via said second bus; v. means responsive to said request message receiving means for receiving said memory response message from said second bus and for modifying said memory response message to contain said first identification information; vi. means for transmitting said modified memory response message to said subsystem via said first bus; vii. means in said subsytem for routing said modified memory response message to one of said input/output means identified by said first identification information.

Claim 11

In a data processing system including first and second time-shared busses each having a plurality of addressable ports, a system comprising in combination: (a) a memory subsystem connected to a first port of said second bus; (b) a subsystem connected to a second port of said first bus, said subsystem including i. a plurality of input/output means for transmitting a request message to said first bus; ii. means for providing first identification information in said request message, said identifying information representing a one of said input/output means from which said request message is transmitted; (c) means coupled to said first and second busses, respectively, for routing said request message from said first bus to said second bus and routing any memory response message produced in response to said request message by said memory subsystem from said second bus to said first bus, said routing means including i. means for receiving said request message from said first bus and determining if said request message requires a response from said memory subsystem; ii. means responsive to said request message receiving means for removing said first identification information from said request message and temporarily storing said first identification information; iii. means for modifying said request message to contain second identification information representing an addressable port on said second bus and the location of said stored first identification information in said responsive means if said request message requires a response from said memory subsystem; iv. means for transmitting said modified request message to said memory subsystem via said second bus; v. means responsive to said request message receiving means for receiving said memory response message from said second bus and for modifying said memory response message to contain said first identification information; vi. means for transmitting said modified memory response message to said subsystem via said first bus; vii. means in said subsytem for routing said modified memory response message to one of said input/output means identified by said first identification information.

Claim 14

The method of claim 10 further including the steps (a) generating a memory response message in response to said modified request message, said memory response message containing said second source code and said second identification information; (b) transmitting said memory response message along said second bus through said second port of said second bus in response to said second source code; and (c) modifying said memory response message by inserting said stored first source code and said stored identification code into said memory response message.

Claim 15

The method of claim 11 further including the step of transmitting said modified memory response message via said first port to said subsystem in response to said first destination code.

Claim 16

The method of claim 12 further including the step of transmitting said modified memory response message along said input/output path in response to said first identification code in said modified memory response message.

Claim 17

The method of claim 12 further including the step of locating said stored first source code and said stored first identification information in response to said second identification information in said memory response message.

Claim 18

The method of claim 10 further including the step of determining whether said request message requires a response prior to step (c).

Claim 19

In a data processing system including first and second busses each having a plurality of addressable ports, a system comprising in combination; (a) a memory subsystem connected to a first port of said second bus; (b) a subsystem connected to a second port of said first bus, said subsystem including input/output means for transmitting a request message to said first bus, and means for inserting first identification information into said request message identifying said subsystem; and (c) means coupled to said first and second busses, respectively, for routing said request message from said first bus to said second bus and routing any memory response message produced in response to said request message by said memory subsystem from said second bus to said first bus, said routing means including i. means for receiving said request message from said first bus and determining if said request message requires a response from said memory subsystem; ii. means for temporarily storing said first identification information; iii. means responsive to said request message receiving means for modifying said request message to contain second identification information representing an addressable port on said second bus and the location of said stored first identification information in said means for temporarily storing; and iv. means for transmitting said modified request message to said memory subsystem via said second bus.

Claim 20

In a data processing system including first and second busses each having a plurality of addressable ports, a system comprising in combination; (a) a memory subsystem connected to a first port of said second bus; (b) a subsystem connected to a second port of said first bus, said subsystem including input/output means for transmitting a request message to said first bus, and means for inserting first identification information into said request message identifying said subsystem; and (c) means coupled to said first and second busses, respectively, for routing said request message from said first bus to said second bus and routing any memory response message produced in response to said request message by said memory subsystem from said second bus to said first bus, said routing means including i. means for receiving said request message from said first bus and determining if said request message requires a response from said memory subsystem; ii. means for temporarily storing said first identification information; iii. means responsive to said request message receiving means for modifying said request message to contain second identification information representing an addressable port on said second bus and the location of said stored first identification information in said means for temporarily storing; and iv. means for transmitting said modified request message to said memory subsystem via said second bus.