US4173739A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Overload detecting circuit for a PWM amplifier
Assignee: Sony Corp
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Filing: 1978-09-18
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Granted: 1979-11-06
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Expires: 1998-09-18
Abstract
Abstract An overload detecting circuit for a PWM amplifier includes an output current detecting circuit and an output voltage detecting circuit. The output of the output voltage detecting circuit is supplied to a rectifying circuit having a discharge time constant determined by the cut-off frequency of a low pass filter as a demodulator of the PWM amplifier. A comparison circuit is provided to produce an overload indicative signal in response to the comparison result between the outputs of the rectifying circuit and of the output current detecting circuit.
Inventors
- 👤 Tadao Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 03:43
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/20; H03F3/21; H03F3/217; H03F1/00; H03F1/52; H03F2200/00; H03F2200/426
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
175 words
An overload detecting circuit for a PWM amplifier comprising: (a) a DC voltage source having a pair of terminals; (b) first and second switching means connected in series between the terminals of said DC voltage source; (c) signal input means for ON/OFF controlling said first and second switching means, alternatively, in response to an input pulse signal; (d) a low pass filter connected between the connection point of said first and second switching means and an output terminal adapted to be connected with a load; (e) first detecting means for detecting an output current flowing through said first switching means; (f) second detecting means for detecting an output voltage produced at said output terminal; (g) first rectifying means connected to said second detecting means and having a discharge time constant circuit determined by the cut-off frequency of said low pass filter; and (h) first comparing means for comparing the outputs of said first detecting means and of said first rectifying means and for producing an overload indicative signal in response to the comparison result therebetween.
Claim 2
Dependent Claim
175 words
An overload detecting circuit for a PWM amplifier comprising: (a) a DC voltage source having a pair of terminals; (b) first and second switching means connected in series between the terminals of said DC voltage source; (c) signal input means for ON/OFF controlling said first and second switching means, alternatively, in response to an input pulse signal; (d) a low pass filter connected between the connection point of said first and second switching means and an output terminal adapted to be connected with a load; (e) first detecting means for detecting an output current flowing through said first switching means; (f) second detecting means for detecting an output voltage produced at said output terminal; (g) first rectifying means connected to said second detecting means and having a discharge time constant circuit determined by the cut-off frequency of said low pass filter; and (h) first comparing means for comparing the outputs of said first detecting means and of said first rectifying means and for producing an overload indicative signal in response to the comparison result therebetween.
Claim 3
Dependent Claim
37 words
An overload detecting circuit for a PWM amplifier according to claim 1, in which the discharge time constant is larger than the time constant determined by the reciprocal of the cut-off frequency of said low pass filter.
Claim 4
Dependent Claim
61 words
An overload detecting circuit for a PWM amplifier according to claim 2, in which said first detecting means comprises first, second and third resistors, said first resistor being connected between one of the terminals of said DC voltage source and said first switching means, a series connection of said second and third resistors being connected in parallel with said first resistor.
Claim 5
Dependent Claim
114 words
An overload detecting circuit for a PWM amplifier according to claim 3, in which said rectifying means comprises a series circuit of a first diode and first capacitor, said series circuit being connected between said output terminal and a reference point; and a series circuit of fourth and fifth resistors, said series circuit being connected between the connection point of said second and third resistors and said second terminal of said DC voltage source, the connection point of said fourth and fifth resistors being connected to the connection point of said first diode and first capacitor, and said first capacitor and said fifth resistor forming said discharge time constant circuit of said rectifying means.
Claim 6
Dependent Claim
58 words
An overload detecting circuit for a PWM amplifier according to claim 4, in which said first comparing means comprises a first switching transistor having base, emitter and collector, the base and emitter circuit of which is connected across said third resistor and the collector of which produces said overload indicative signal when said first switching transistor becomes conductive.
Claim 7
Dependent Claim
45 words
An overload detecting circuit for a PWM amplifier according to claim 5, which further includes input attenuating means connected to said signal input means and controlled by said first switching transistor so as to decrease the input signal when said first switching transistor becomes conductive.
Claim 8
Dependent Claim
23 words
An overload detecting circuit for a PWM amplifier according to claim 6, in which said input attenuating means comprises a field effect transistor.
Claim 9
Dependent Claim
102 words
An overload detecting circuit for a PWM amplifier according to claim 5, which further includes a third detecting means for detecting an output current flowing through said second switching means, fourth detecting means for detecting an output voltage produced at said output terminal, second rectifying means connected to said fourth detecting means and having a discharge time constant circuit determined by the cut-off frequency of said low pass filter, and second comparing means for comparing the outputs of said third detecting means and of said second rectifying means and for controlling said first switching transistor in response to the comparison result therebetween.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-11-05 | 1983-05-07 | 1983-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-11-05 | 1987-05-07 | 1987-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-11-05 | 1991-05-07 | 1991-11-06 | $7700.00 | Window Closed / Lapsed |