US4153906A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit using an insulated gate field effect transistor
Assignee: Fujitsu Ltd
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Filing: 1977-11-22
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Granted: 1979-05-08
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Expires: 1997-11-22
Abstract
Abstract This disclosure relates to an integrated circuit using an insulated gate field effect transistor of the punch-through type for use in high speed electronic computation. Until now the punch-through phenomena has been considered a defect in the insulated gate field effect transistor. However, the effective utilization of the punch-through phenomena is achieved by using a specially designed insulated gate field effect transistor having a selected structure or material.
Inventors
- 👤 Masaichi Shinoda
- 👤 Tetsuo Nakamura
- 👤 Minoru Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/202; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D84/00; H10D84/80; H10D84/82; H10D84/83
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
166 words
An integrated circuit using an insulated gate field effect transistor of the punch-through type, in which said insulated gate field effect transistor is formed in a semiconductor substrate of a predetermined conductivity type and has a source electrode, gate electrode, and a drain electrode, said source and drain electrodes located in different regions of the surface of said substrate, and said gate electrode located on a gate insulating layer formed on said semiconductor substrate between said source and drain electrodes, wherein the impurity concentration in said semiconductor substrate, and the channel length between said source and drain electrodes, and the thickness of said gate insulating layer are selected such that said insulated gate field effect transistor is rendered non-conductive in the absence of a gate voltage applied to said gate electrode, and said insulated gate field effect transistor is rendered conductive due to the punch-through effect between said source and drain electrodes when a gate voltage of a predetermined polarity is applied to said gate electrode.
Claim 2
Dependent Claim
166 words
An integrated circuit using an insulated gate field effect transistor of the punch-through type, in which said insulated gate field effect transistor is formed in a semiconductor substrate of a predetermined conductivity type and has a source electrode, gate electrode, and a drain electrode, said source and drain electrodes located in different regions of the surface of said substrate, and said gate electrode located on a gate insulating layer formed on said semiconductor substrate between said source and drain electrodes, wherein the impurity concentration in said semiconductor substrate, and the channel length between said source and drain electrodes, and the thickness of said gate insulating layer are selected such that said insulated gate field effect transistor is rendered non-conductive in the absence of a gate voltage applied to said gate electrode, and said insulated gate field effect transistor is rendered conductive due to the punch-through effect between said source and drain electrodes when a gate voltage of a predetermined polarity is applied to said gate electrode.
Claim 3
Dependent Claim
36 words
An integrated circuit using an insulated gate field effect transistor of the punch-through type in accordance with claim 10 wherein said insulated gate field effect transistor is connected to a depletion type field effect transistor load.
Claim 4
Dependent Claim
75 words
An integrated circuit using an insulated gate field effect transistor of the punch-through type in accordance with claim 2 wherein said insulated gate field effect transistor is arranged in a complementary circuit which is formed of a N-channel punch-through type insulated gate field effect transistor and a series connected P-channel punch-through type insulated gate field effect transistor, the gates of said N- and P-channel punch-through type insulated gate field effect transistors being connected in parallel.
Claim 5
Dependent Claim
41 words
An integrated circuit using an insulated gate field effect transistor of the punch-through type in accordance with claim 1 wherein said insulated gate field effect transistor is connected to another punch-through type insulated gate field effect transistor used as a load.
Claim 6
Dependent Claim
75 words
An integrated circuit using an insulated gate field effect transistor of the punch-through type in accordance with claim 1 wherein said insulated gate field effect transistor is arranged in a complementary circuit which is formed of a N-channel punch-through type insulated gate field effect transistor and a series connected P-channel punch-through type insulated gate field effect transistor, the gates of said N- and P-channel punch-through type insulated gate field effect transistors being connected in parallel.
Claim 7
Dependent Claim
37 words
An integrated circuit in accordance with claim 1, wherein said insulated gate field effect transistor has a range of impurity atom concentration in its substrate of from 7×10 15 cm -3 to 1.2×10 16 cm -3 .
Claim 8
Dependent Claim
31 words
An integrated circuit in accordance with claim 6, wherein said insulated gate field effect transistor has a range of distance between its source and its drain of from 1μ to 1.5μ.
Claim 9
Dependent Claim
29 words
An integrated circuit in accordance with claim 6, wherein said insulated gate field effect transistor has a range of thickness of its gate insulator of from 350A to 1000A.
Claim 10
Dependent Claim
31 words
An integrated circuit in accordance with claim 1, wherein said insulated gate field effect transistor has a range of distances between its source and its drain of from 1μ to 1.5μ.
Claim 11
Dependent Claim
29 words
An integrated circuit in accorance with claim 1, wherein said insulated gate field effect transistor has a range of thickness of its gate insulator of from 350A to 1000A.
Claim 12
Dependent Claim
31 words
An integrated circuit in accordance with claim 10, wherein said insulated gate field effect transistor has a range of distance between its source and its drain of from 1μ to 1.5μ.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-07 | 1982-11-06 | 1983-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-07 | 1986-11-06 | 1987-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-07 | 1990-11-06 | 1991-05-08 | $7700.00 | Window Closed / Lapsed |