Circuit arrangement for the transmission of digital signals between subscriber stations of a time multiplex telecommunications network

Claim 1

A circuit arrangement for the transmission of signals between a subscriber station having an input for receiving analog signals and an output for emitting analog signals and a two-wire multiplex line operated as a four-wire multiplex line in a time division multiplex telecommunications system having a plurality of such subscriber stations and other multiplex lines, comprising: a coder/decoder arrangement for each subscriber station including a first input connected to the output of the subscriber station to receive analog signals therefrom, a first output connected to the input of the subscriber station to feed analog signals thereto, a second input for receiving digital signals, a second output for emitting digital signals, conversion means connected to said first and second inputs and to said first and second outputs for converting received analog and digital signals to the opposite type of signals, and a control input for receiving first control pulses to effect an input of digital signals at said second input and an output of digital signals at said output; a receiving memory for each subscriber station including an input connected to the multiplex line, an output connected to said second input of said coder/decoder arrangement and a control input for receiving second control pulses to effect an input of digital information from the time multiplex line, each of said receiving memories comprising a cyclically triggerable shift register; a cyclically triggerable shift register transmitting memory for each subscriber station including an input connected to said second output of said coder/decoder arrangement, an output connected to the multiplex line, a control input for receiving third control pulses to effect transmission of digital information on the multiplex line; and control circuit means connected to said coder/decoder arrangement control input, to said receiving memory control input and to said transmitting memory control input for providing the first, second and third control pulses thereto, each of said control pulses having a predetermined number of bit pulses corresponding in number to the number of bit pulses forming a digital word in the transmission system, the control pulses time-spaced such that the bit pulses of the first control pulse occur at times which lie in the same pulse time raster defined by the bit pulses of the second and third control pulses assigned to the receiving and transmitting memories, said control means including means for generating respective third control pulses for said transmitting memories including a circulating memory connected to said transmitting memories and storing the addresses thereof, said control circuit comprising means for generating respective second control pulses for said receiving memories including a circulating memory connected to and storing the addresses of said receiving memories.