← Back to Patent Explorer
US4121296A Expired / Lapsed US ⏱️ 0.0 years remaining

Digital signal processing arrangement

Assignee: US Philips Corp
•
Filing: 1977-06-20
•
Granted: 1978-10-17
•
Expires: 1997-06-20
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Digital signal processing arrangement such as a digital filter for computing output signal samples which are each equal to the sum of products of a given plurality of pairs (for example N) of input signal samples. One of the input signal samples of the pair is, for example, formed each time by a sample x(n) of a digital signal to be filtered, the other input signal sample of the pair by a filter coefficient z(n), wherein either the sample x(n) or the filter coefficient z(n) can assume only a limited number of values 0, ±A 1 , ±A 2 , . . . ±A M , M being much smaller than N. In the case x(n) can assume only this limited number of values, z(n) is first multiplied, owing to the x(n) belonging to the pair, by the sign of x(n) for generating a product of the form z(n). sgn [x(n)]. In-dependent of the magnitude of n(n) this product is applied to an accumulator which corresponds with this magnitude of x(n). N products have been applied to one of the M accumulators the partial sums stored therein are multiplied by the magnitude |x(n)| corresponding therewith and the products obtained are added together.

Inventors

  • 👤 Wilfred Andre Maria Snijders
  • 👤 Nicolaas Alphonsus Maria Verhoeckx
  • 👤 Petrus Josephus van Gerwen
  • 👤 Hendrik Arie VAN Essen

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 16:22
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/15; H; H03; H03H; H03H17/00; H03H17/02; H03H17/0223; H03H17/0227; H03H17/0233; H04; H04L; H04L27/00; H04L27/02; H04L27/04

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 242 words
A digital signal processing arrangement for generating digital output signal samples y(n) which are each formed by the sum of a given plurality of first signal samples x(n) which are each modified by one of a plurality of second signal samples z(n), comprising: first means for serially supplying first signal samples x(n); second means for serially supplying second signal samples z(n); multiplying means having an input circuit and an output circuit; first coupling means for coupling the input circuit of the multiplying means to the first and second means comprising: means coupled to said first and second means for modifying each of the second signal samples z(n) by an algebraic coefficient sgn [x(n)] which represents the polarity of the first signal sample x(n) associated with the signal sample z(n), for generating signal samples of the form z(n) · sgn [x(n)]; a plurality of auxiliary accumulators which each correspond to one of the magnitudes [x(n)] of the first signal samples x(n) and whose outputs are coupled to the input circuit of the multiplying means for multiplying the contents of each of the auxiliary accumulators by the algebraic factor [x(n)] corresponding therewith; adder means coupled to said multiplying means; and second coupling means which are controlled by said first signal samples x(n) for applying the signal sample z(n) · sgn [x(n)] to that auxiliary accumulator which corresponds with the magnitude [x(n)] of the first signal sample x(n) associated with the second signal sample z(n).
Claim 2
Dependent Claim 242 words
A digital signal processing arrangement for generating digital output signal samples y(n) which are each formed by the sum of a given plurality of first signal samples x(n) which are each modified by one of a plurality of second signal samples z(n), comprising: first means for serially supplying first signal samples x(n); second means for serially supplying second signal samples z(n); multiplying means having an input circuit and an output circuit; first coupling means for coupling the input circuit of the multiplying means to the first and second means comprising: means coupled to said first and second means for modifying each of the second signal samples z(n) by an algebraic coefficient sgn [x(n)] which represents the polarity of the first signal sample x(n) associated with the signal sample z(n), for generating signal samples of the form z(n) · sgn [x(n)]; a plurality of auxiliary accumulators which each correspond to one of the magnitudes [x(n)] of the first signal samples x(n) and whose outputs are coupled to the input circuit of the multiplying means for multiplying the contents of each of the auxiliary accumulators by the algebraic factor [x(n)] corresponding therewith; adder means coupled to said multiplying means; and second coupling means which are controlled by said first signal samples x(n) for applying the signal sample z(n) · sgn [x(n)] to that auxiliary accumulator which corresponds with the magnitude [x(n)] of the first signal sample x(n) associated with the second signal sample z(n).

References Cited (Backward Citations)

US3522546A Cited
US3979701A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-10-16 1982-04-17 1982-10-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-10-16 1986-04-17 1986-10-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-10-16 1990-04-17 1990-10-17 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag