US4101761A
Expired / Lapsed
US
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Timing pulse generator
Assignee: Pacific Western Systems Inc
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Filing: 1976-11-26
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Granted: 1978-07-18
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Expires: 1996-11-26
Abstract
Abstract A timing pulse generator for testing electronic components such as semiconductor memories, which tests require time accuracy and repeatability. A number of registers are provided for registering digital words which correspond to timing pulses to be generated. Each word includes information in a first portion as to the coarse start time of a particular pulse and information in a second portion as to the fine start time of the pulse. A counter circuit is provided with means for starting and stepping the counter in pedetermined increments through a plurality of states. A digital comparator compares the state of the counter with the coarse start time portion of the word stored in the register and generates an output pulse when the two coincide. A digitally controlled variable delay circuit is provided corresponding to each register. An output from the register corresponding to the fine start time portion of the word sets the amount of delay introduced by the delay circuit. The output pulse from the digital comparator is applied to the delay circuit such that the pulse is delayed by an amount determined by the fine start time information in the word stored in the register. The counter start control means enables automatic switching between triggered and gated modes for single cycle or continuous cycle operation of the counter without false triggering of the counter.
Inventors
- 👤 Wayne R. Merryman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 16:50
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31922; G01R31/31903; G01R31/31908; G01R31/3191; H; H03; H03K; H03K21/00; H03K21/38; H03K3/00; H03K3/02; H03K3/027; H03K3/03; H03K3/0307; H03K5/00; H03K5/13; H03K5/131; H03K5/15; H03K5/15013; H03K5/1502
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
245 words
In a timing circuit: register means for registering a word having a first portion and a second portion and for providing said word at an output of said registering means; a counter for providing an output; clock means stepping said counter in predetermined increments of time through a plurality of states; comparator means responsive to said counter output and to said first word portion of said output of said registering means for comparing said first portion of said word and the state of said counter and for generating a comparator output at an output of said comparator means when the two coincide; and variable delay means having a plurality of predetermined selectable incremental delay values of time independent of said time increments of said clock means, said incremental delay values of time being of shorter duration than the time increments of said clock means and being responsive to the output of said comparator means and to said second portion of said output word of said register means for selecting the incremental value of said delay in accordance with information in said second portion of said word and for producing a timing pulse output at the end of said selected incremental amount of said delay the starting time of said timing pulse output being thereby specified by information in said first portion of said word output of said register means and as further incrementally delayed in accordance with information in said second portion of said word.
Claim 2
Dependent Claim
245 words
In a timing circuit: register means for registering a word having a first portion and a second portion and for providing said word at an output of said registering means; a counter for providing an output; clock means stepping said counter in predetermined increments of time through a plurality of states; comparator means responsive to said counter output and to said first word portion of said output of said registering means for comparing said first portion of said word and the state of said counter and for generating a comparator output at an output of said comparator means when the two coincide; and variable delay means having a plurality of predetermined selectable incremental delay values of time independent of said time increments of said clock means, said incremental delay values of time being of shorter duration than the time increments of said clock means and being responsive to the output of said comparator means and to said second portion of said output word of said register means for selecting the incremental value of said delay in accordance with information in said second portion of said word and for producing a timing pulse output at the end of said selected incremental amount of said delay the starting time of said timing pulse output being thereby specified by information in said first portion of said word output of said register means and as further incrementally delayed in accordance with information in said second portion of said word.
Claim 3
Dependent Claim
53 words
The combination in accordance with claim 1 wherein said registering means further comprises at least two registers, each register capable of storing a word and enabling means for activating only one of said registers at a time for providing the word stored in said one register at said output of said registering means.
Claim 4
Dependent Claim
55 words
The apparatus of claim 1 wherein said variable delay means comprises a plurality of serially arranged delay stage means each delay stage means providing a predetermined incremental delay value when enabled, and said serially arranged delay stage means being selectively enabled by information in said second portion of said output word of said registering means.
Claim 5
Dependent Claim
54 words
The apparatus of claim 3 wherein individual ones of said delay stage means includes a printed circuit delay element having a predetermined incremental value of time delay and means responsive to information in said second portion of said output word of said registering means for selectively enabling respective ones of said delay stage means.
Claim 6
Dependent Claim
239 words
In a timing system for generating a plurality of timed pulses comprising: a plurality of channels, each channel comprising means for registering a word having a first portion and a second portion; a counter for providing an output; clock means for stepping said counter in predetermined increments of time through a plurality of states; comparator means in each of said channels responsive to said counter and said registering means within said channel for comparing said first portion of said word with the state of said counter and for generating a pulse when the two coincide; and delay means in each channel having a plurality of of predetermined selectable incremental delay values of time independent of said time increments of a clock means, said incremental delay values of time being of shorter duration than the time increments of said clock means and being responsive to the output of said comparator means and to said second portion of said output word of said register means for selecting the incremental value of said delay in accordance with information in said second portion of word and for producing a timing pulse output at the end of said selected incremental amount of said delay, the starting time of said timing pulse being thereby specified by information in said first portion of said word output of said register means and as further incrementally delayed in accordance with information in said second portion of said word.
Claim 7
Dependent Claim
239 words
In a timing system for generating a plurality of timed pulses comprising: a plurality of channels, each channel comprising means for registering a word having a first portion and a second portion; a counter for providing an output; clock means for stepping said counter in predetermined increments of time through a plurality of states; comparator means in each of said channels responsive to said counter and said registering means within said channel for comparing said first portion of said word with the state of said counter and for generating a pulse when the two coincide; and delay means in each channel having a plurality of of predetermined selectable incremental delay values of time independent of said time increments of a clock means, said incremental delay values of time being of shorter duration than the time increments of said clock means and being responsive to the output of said comparator means and to said second portion of said output word of said register means for selecting the incremental value of said delay in accordance with information in said second portion of word and for producing a timing pulse output at the end of said selected incremental amount of said delay, the starting time of said timing pulse being thereby specified by information in said first portion of said word output of said register means and as further incrementally delayed in accordance with information in said second portion of said word.
Claim 8
Dependent Claim
41 words
The combination in accordance with claim 5 wherein said stepping means includes starting means and wherein at least one of said channels is connected to said starting means to thereby initiate the restarting of said starting means at a predetermined time.
Claim 9
Dependent Claim
132 words
The combination in accordance with claim 6 wherein said starting means includes: a flip-flop having a first input for turning said flip-flop ON, a second input for tuning said flip-flop OFF, and an output; means connected to said first input for turning on said flip-flop from an external trigger source and from said one channel; a stop signal line connected to said second input for turning OFF said flip-flop when said stop signal line is energized; means for combining said stop line with the output of said flip-flop to produce a gate signal upon the conditions that said flip-flop is on and said stop signal line is disenergized; and wherein said stepping means further comprises: a gated oscillator having a gate input connected to the gate signal produced by said combining means.
References Cited (Backward Citations)
US3371334A
Cited
US3569677A
Cited
US3824378A
Cited
US3840174A
Cited
US3947664A
Cited
US3981440A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-17 | 1982-01-16 | 1982-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-17 | 1986-01-16 | 1986-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-17 | 1990-01-16 | 1990-07-18 | $7700.00 | Window Closed / Lapsed |