Electronic countermeasure sequence timer

Claim 1

A random period time sequencer for causing the device to which it is coupled to pseudo-randomly alternate between its operating modes, comprising: a power supply; a digital shift register providing a plurality of outputs consisting of ones and zeros in the form of electrical signals; an initializing circuit coupled to said power supply and having an output coupled to said shift register for providing an electrical signal to said shift register establishing predetermined initial conditions in said shift register; a variable period clock coupled to said initializing circuit; a zeros detector coupled to an output of said shift register for detecting the totality of zeros in the output and providing an output indicative thereof; a ones detector coupled to an output of said shift register for detecting the totality of ones in the output and providing an output indicative thereof; at least one code generator coupled to an output of said shift register for generating a digital pattern in response to the coincidence of preselected bits therein; a generator cycle control coupled to said ones and zeros detectors, for receiving their outputs, and to said at least one generator for controlling its pattern cycle; a cycle selector for selectively coupling said at least one code generator to said shift register; and an interface driver coupled to the output of said shift register for providing the sequencer output in response thereto.