Fast and normal rate instruction fetching

Claim 2

In a computer system having fixed length machine cycles and where instructions consisting of a plurality of segments are fetched from storage in a timed relationship to said fixed length machine cycles by fetching segments of an instruction successively to completely fetch an instruction, said instruction including first and second predetermined types of instructions, the improvement comprising: means for fetching a first segment of an instruction during a first portion of said fixed length machine cycle to enable determination of the type of instruction being fetched, instruction analyzing means for analyzing said first segment and generating one type of signal when the type of instruction being fetched is analyzed as being said first predetermined type of instruction and generating another type of signal when the type of instruction being fetched is analyzed as being said second predetermined type of instruction, and means responsive to said instruction analyzing means generating said one type of signal for fetching at least another segment of said instruction during the same fixed length machine cycle that was used for fetching said first segment.

Claim 3

The computer system of claim 1 wherein said first predetermined type of instruction is a one address direct instruction defined by a first segment and having at least a second segment containing encoded bits for representing a location in said storage.

Claim 4

The computer system of claim 1 wherein said first predetermined type of instruction is a one address indexed instruction defined by a first segment and having at least a second segment containing encoded bits for representing an address indexing value.

Claim 5

The computer system of claim 1 wherein said first predetermined type of instruction is a two address direct instruction defined by a first segment and having at least second and third segments each containing encoded bits for representing individual locations in said storage.

Claim 6

The computer system of claim 1 wherein said first predetermined type of instruction is a two address instruction with one address direct and one address indexed defined by a first segment and having at least a second segment containing encoded bits for representing a location in said storage and a third segment containing encoded bits for representing an indexing value.

Claim 7

The computer system of claim 1 wherein said first predetermined type of instruction is a two address indexed instruction defined by a first segment and having at least second and third segments each containing encoded bits for representing individual locations in said storage and a fourth segment containing encoded bits for representing an indexing value.

Claim 8

In a computer system having an addressable storage for storing instructions consisting of segments where each segment is stored at an addressable location, and a central processing unit including timing means for providing timing signals defining fixed length machine cycles, and addressing means connected under control of said timing means and to said storage for addressing said storage to fetch a segment of an instruction whereby an instruction is fetched by successive fetches of segments, the improvement comprising: means within said timing means for causing said addressing means to address said storage during a first portion of said fixed length machine cycle so as to fetch a first segment of an instruction, means responsive to a timing signal from said timing means for providing address modification signals to said addressing means for modifying the storage address of the segment being fetched during said first portion of a machine cycle, instruction analyzing means connected to said storage and under control of said timing means for receiving said first segment of an instruction for analyzation thereof during said first portion of said fixed length machine cycle and including means for generating a signal as a result of said analyzation indicating the type of instruction being fetched, and means for providing a signal to said timing means in response to said instruction analyzing means generating a signal indicating a first predetermined type of instruction for causing said addressing means to address said storage during a second portion of said fixed length machine cycle during which said instruction analyzing means received said first segment of an instruction.

Claim 9

In a computer system having an addressable storage for storing instructions consisting of segments where each segment is stored at an addressable location, and a central processing unit including timing means for providing timing signals defining fixed length machine cycles, and addressing means connected under control of said timing means and to said storage for addressing said storage to fetch a segment of an instruction whereby an instruction is fetched by successive fetches of segments, the improvement comprising: means within said timing means for causing said addressing means to address said storage during a first portion of said fixed length machine cycle so as to fetch a first segment of an instruction, means responsive to a timing signal from said timing means for providing address modification signals to said addressing means for modifying the storage address of the segment being fetched during said first portion of a machine cycle, instruction analyzing means connected to said storage and under control of said timing means for receiving said first segment of an instruction for analyzation thereof during said first portion of said fixed length machine cycle and including means for generating a signal as a result of said analyzation indicating the type of instruction being fetched, and means for providing a signal to said timing means in response to said instruction analyzing means generating a signal indicating a first predetermined type of instruction for causing said addressing means to address said storage during a second portion of said fixed length machine cycle during which said instruction analyzing means received said first segment of an instruction.

Claim 10

In a stored program computer system having storage for storing instructions consisting of segments, said instructions being of first and second types, means for fetching instructions segment by segment during fixed length machine cycles, each instruction requiring at least two instruction segment fetches to completely fetch an instruction, the improvement comprising: means for providing signals to said means for fetching instructions to inititate an instruction segment fetch at the beginning of said fixed length machine cycle, indicating means connected to receive said instruction segment fetched at the beginning of said machine cycle for generating a signal indicating the type of instruction being fetched as a result of analyzing the segment fetched, and means for controlling signals to said means for fetching instructions to initiate an additional instruction segment fetch within said fixed length machine cycle having said instruction segment fetch at the beginning thereof in response to said signal generated by said indicating means indicating that the instruction being fetched is said first predetermined type.

Claim 11

In a stored program computer system having storage for storing instructions consisting of segments, said instructions being of first and second types, means for fetching instructions segment by segment during fixed length machine cycles, each instruction requiring at least two instruction segment fetches to completely fetch an instruction, the improvement comprising: means for providing signals to said means for fetching instructions to inititate an instruction segment fetch at the beginning of said fixed length machine cycle, indicating means connected to receive said instruction segment fetched at the beginning of said machine cycle for generating a signal indicating the type of instruction being fetched as a result of analyzing the segment fetched, and means for controlling signals to said means for fetching instructions to initiate an additional instruction segment fetch within said fixed length machine cycle having said instruction segment fetch at the beginning thereof in response to said signal generated by said indicating means indicating that the instruction being fetched is said first predetermined type.

Claim 12

In a computer system having fixed length machine cycles, an addressable storage for storing instructions, each instruction consisting of segments with each segment stored at an addressable location, said instructions including first and second predetermined types of instructions, addressing means connected for addressing said storage, storage control means connected for controlling reading from and writing into said storage during said machine cycles, an address source connected to provide addresses to said addressing means, instruction analyzing means connected to receive first segments of instructions read from storage for generating signals which indicate the type of instruction being fetched, timing means for providing timing signals defining said fixed length machine cycles and connected to provide said timing signals to said storage control means, to said address source, to said instruction analyzing means, the improvement comprising: means for modifying addresses from said address source while said storage control means is controlling reading of first segments of instructions out of storage to provide modified addresses to said addressing means, and means responsive to signals from said analyzing means indicating first predetermined types of instructions for providing signals to said storage control means to cause reading from said storage whereby two instruction segments are read from said storage within a single fixed length machine cycle for said first predetermined types of instructions.

Claim 13

In a computer system having fixed length machine cycles, an addressable storage for storing instructions, each instruction consisting of segments with each segment stored at an addressable location, said instructions including first and second predetermined types of instructions, addressing means connected for addressing said storage, storage control means connected for controlling reading from and writing into said storage during said machine cycles, an address source connected to provide addresses to said addressing means, instruction analyzing means connected to receive first segments of instructions read from storage for generating signals which indicate the type of instruction being fetched, timing means for providing timing signals defining said fixed length machine cycles and connected to provide said timing signals to said storage control means, to said address source, to said instruction analyzing means, the improvement comprising: means for modifying addresses from said address source while said storage control means is controlling reading of first segments of instructions out of storage to provide modified addresses to said addressing means, and means responsive to signals from said analyzing means indicating first predetermined types of instructions for providing signals to said storage control means to cause reading from said storage whereby two instruction segments are read from said storage within a single fixed length machine cycle for said first predetermined types of instructions.

Claim 14

In a computer system having fixed length machine cycles and where instructions consisting of a plurality of segments are fetched from storage in a timed relationship to said fixed length machine cycles by fetching segments of an instruction successively to completely fetch an instruction, said instructions including first and second predetermined types of instructions, the improvement comprising: instruction fetching means for fetching segments of instructions and initially operable to fetch a first segment of an instruction during a first portion of said fixed length machine cycle and operable to fetch a second segment of an instruction during the same fixed length machine cycle for fetching said first segment upon receiving a signal indicating that the instruction being fetched is not said second type of instruction and rendered inoperable to fetch a second segment of an instruction during the same fixed length machine cycle for fetching said first segment upon receiving a signal indicating that the instruction being fetched is said second type of instruction, instruction analyzing means for analyzing said first segment of an instruction and generating one type of signal indicating that the type of instruction being fetched is not said second predetermined type of instruction and generating another type of signal indicating that the instructio being fetched is said second predetermined instruction, and means for applying said one and another types of signals to said instruction fetching means.

Claim 15

In a computer system having fixed length machine cycles and where instructions consisting of a plurality of segments are fetched from storage in a timed relationship to said fixed length machine cycles by fetching segments of an instruction successively to completely fetch an instruction, said instructions including first and second predetermined types of instructions, the improvement comprising: instruction fetching means for fetching segments of instructions and initially operable to fetch a first segment of an instruction during a first portion of said fixed length machine cycle and operable to fetch a second segment of an instruction during the same fixed length machine cycle for fetching said first segment upon receiving a signal indicating that the instruction being fetched is not said second type of instruction and rendered inoperable to fetch a second segment of an instruction during the same fixed length machine cycle for fetching said first segment upon receiving a signal indicating that the instruction being fetched is said second type of instruction, instruction analyzing means for analyzing said first segment of an instruction and generating one type of signal indicating that the type of instruction being fetched is not said second predetermined type of instruction and generating another type of signal indicating that the instructio being fetched is said second predetermined instruction, and means for applying said one and another types of signals to said instruction fetching means.

Claim 16

In a computer system having fixed length machine cycles, an addressable storage for storing instructions, each instruction consisting of segments with each segment stored at an addressable location, said instructions including first and second predetermined types of instructions, addressing means connected for addressing said storage, storage control means connected for controlling reading from and writing into said storage during said fixed length meache cycles, an address source connected to provide addresses to said addressing means, instruction analyzing means connected to receive first segments of instructions read from storage and generate signals indicating that the instruction being fetched is not said second predetermined type of instruction, timing means for providing timing signals defining said fixed length machine cycles and connected to provide said timing signals to said storage control means, to said address source, to said instruction analyzing means, the improvement comprising: means for modifying addresses from said address source while said storage control means is controlling reading of said first segments from storage and providing modified addresses to said addressing means, and means responsive to signals from said analyzing means indicating that the instructions being fetched are not said second predetermined type of instruction for providing signals to said storage control means to cause additional reading of said storage during the same fixed length machine cycles for fetching said first segments whereby two instruction segments are read from said storage within a single machine cycle for said first predetermined types of instructions.

Claim 17

In a computer system having fixed length machine cycles, an addressable storage for storing instructions, each instruction consisting of segments with each segment stored at an addressable location, said instructions including first and second predetermined types of instructions, addressing means connected for addressing said storage, storage control means connected for controlling reading from and writing into said storage during said fixed length meache cycles, an address source connected to provide addresses to said addressing means, instruction analyzing means connected to receive first segments of instructions read from storage and generate signals indicating that the instruction being fetched is not said second predetermined type of instruction, timing means for providing timing signals defining said fixed length machine cycles and connected to provide said timing signals to said storage control means, to said address source, to said instruction analyzing means, the improvement comprising: means for modifying addresses from said address source while said storage control means is controlling reading of said first segments from storage and providing modified addresses to said addressing means, and means responsive to signals from said analyzing means indicating that the instructions being fetched are not said second predetermined type of instruction for providing signals to said storage control means to cause additional reading of said storage during the same fixed length machine cycles for fetching said first segments whereby two instruction segments are read from said storage within a single machine cycle for said first predetermined types of instructions.