High power field effect transistor

Claim 2

A field effect transistor comprising: a gallium arsenide N+ substrate having an N epitaxial layer on one surface thereof, a Schottky barrier layer on the surface of said epitaxial layer opposite from said substrate, said substrate being selectively relieved from the other surface thereof opposite from said epitaxial layer to a depth at least commensurate with its junction with said epitaxial layer but short of said barrier layer to define at least two separated mesas above said epitaxial layer and spaced apart by a region including a portion of said epitaxial layer, terminal contacts on said mesas, a gate terminal structure connected to said barrier layer, and said at least two separated mesas serving as a source and as a drain respectively, the mesa serving as the source having a structurally altered electrically inactive central portion thereby to reduce the gate-to-source capacitance.

Claim 3

A field effect transistor comprising: a body of semiconductor material of one type conductivity, at least two separated mesas of the same semiconductor material as said body and of said one type conductivity, said mesas being disposed on said body and extending outwardly therefrom, said semiconductor mesas being relatively heavily doped with a conductivity-determining dopant material of said one type conductivity compared to said semiconductor body and being spaced apart by a region including a portion of said body, a Schottky barrier layer on the surface of said body opposite from said mesas, terminal contacts on said mesas, a gate terminal structure connected to said barrier layer, and said at least two separated mesas serving as a source and as a drain respectively, the mesa serving as the source having a structurally altered electrically inactive central portion thereby to reduce the gate to source capacitance.

Claim 4

A field effect transistor comprising: a body of semiconductor material of one type conductivity, at least two separated mesas of the same semiconductor material as said body and of said one type conductivity, said mesas being disposed on said body and extending outwardly therefrom, said semiconductor mesas being relatively heavily doped with a conductivity-determining dopant material of said one type conductivity compared to said semiconductor body and being spaced apart by a region including a portion of said body, a Schottky barrier layer on the surface of said body opposite from said mesas, terminal contacts on said mesas, a gate terminal structure connected to said barrier layer, and said at least two separated mesas serving as a source and as a drain respectively, the mesa serving as the source having a structurally altered electrically inactive central portion thereby to reduce the gate to source capacitance.

Claim 5

A field effect transistor comprising: a body of semiconductor material of one type conductivity, at least two separated mesas of the same semiconductor material as said body and of said one type conductivily, said mesas being disposed on said body and extending outwardly therefrom, said semiconductor mesas being relatively heavily doped with a conductivity-determining dopant material of said one type conductivity compared to said semiconductor body and being spaced apart by a region including a portion of said body, a Schottky barrier layer on the surface of said body opposite from said mesas, said at least two separated mesas serving as a source and as a drain respectively, terminal contacts on said mesas, a gate terminal structure connected to said barrier layer, the perimeter of said semiconductor body being inwardly bevelled to a depth commensurate with its junction with the barrier layer, and the barrier layer having a perimeter disposed inwardly with respect to the perimeter of said semiconductor body to reduce the gate to source capacitance.

Claim 6

A field effect transistor comprising: a body of semiconductor material of one type conductivity, at least two separated mesas of the same semiconductor material as said body and of said one type conductivily, said mesas being disposed on said body and extending outwardly therefrom, said semiconductor mesas being relatively heavily doped with a conductivity-determining dopant material of said one type conductivity compared to said semiconductor body and being spaced apart by a region including a portion of said body, a Schottky barrier layer on the surface of said body opposite from said mesas, said at least two separated mesas serving as a source and as a drain respectively, terminal contacts on said mesas, a gate terminal structure connected to said barrier layer, the perimeter of said semiconductor body being inwardly bevelled to a depth commensurate with its junction with the barrier layer, and the barrier layer having a perimeter disposed inwardly with respect to the perimeter of said semiconductor body to reduce the gate to source capacitance.

Claim 7

A field effect transistor comprising: a gallium arsenide N+ substrate having an N epitaxial layer on one surface thereof, a Schottky barrier layer on the surface of said epitaxial layer opposite from said substrate, said substrate being selectively relieved from the other surface thereof opposite from said epitaxial layer to a depth at least commensurate with its junction with said epitaxial layer but short of said barrier layer to define at least two separated mesas above said epitaxial layer and spaced apart by a region including a portion said epitaxial layer, said at least two separated mesas serving as a source and as a drain respectively, terminal contacts on said mesas, a gate terminal structure connected to said barrier layer, the perimeter of said epitaxial layer being relieved to a depth commensurate with its junction with the barrier layer, and the barrier layer having a perimeter disposed inwardly with respect to the perimeter of said epitaxial layer to reduce the gate to source capacitance.

Claim 8

A field effect transistor comprising: a gallium arsenide N+ substrate having an N epitaxial layer on one surface thereof, a Schottky barrier layer on the surface of said epitaxial layer opposite from said substrate, said substrate being selectively relieved from the other surface thereof opposite from said epitaxial layer to a depth at least commensurate with its junction with said epitaxial layer but short of said barrier layer to define at least two separated mesas above said epitaxial layer and spaced apart by a region including a portion said epitaxial layer, said at least two separated mesas serving as a source and as a drain respectively, terminal contacts on said mesas, a gate terminal structure connected to said barrier layer, the perimeter of said epitaxial layer being relieved to a depth commensurate with its junction with the barrier layer, and the barrier layer having a perimeter disposed inwardly with respect to the perimeter of said epitaxial layer to reduce the gate to source capacitance.