Interrupt control system for a microcomputer

Claim 2

An interrupt control system for handling a multiplicity of real time interrupt request signals to a central processing unit of a microcomputer comprising: means including a multiplicity of interrupt control sections each having an assigned level of priority for generating a predetermined interrupt pulse in response to the occurrence of each of said interrupt request signals; means responsive to the level of priority of each interrupt request signal for locking out each interrupt control section to which interrupt request signals of lower priority are applied; means for generating an interrupt instruction for said central processing unit in response to each predetermined interrupt pulse; means for generating an interrupt busy signal of predetermined duration in response to the generation of an interrupt instruction; and means responsive to said interrupt busy signal for inhibiting such multiplicity of interrupt control sections during said predetermined time duration.

Claim 3

An interrupt control system as defined in claim 1 wherein said means for locking out interrupt control sections comprises: means for generating a priority level busy signal in response to the level of priority of each interrupt request signal and gating means responsive to said priority level busy signal for inhibiting each control section having a lower preassigned priority.

Claim 4

An interrupt control system as defined in claim 2 wherein said gating means comprises a priority chain of serially connected AND gates with the AND gate corresponding to the highest level of priority being responsive to said interrupt busy signal.

Claim 5

An interrupt control system as defined in claim 1 further comprising memory means for storing and restoring register and/or flag data supplied from said central processing unit in response to at least one predetermined interrupt instruction including a memory array and a memory control circuit, said memory control circuit comprising: counter means for addressing said memory array; means for setting the direction of said counter means to count up when data is to be read into said array and to count down when data is to be read from said memory array; means for generating increment pulses; means responsive to said increment pulses for incrementing said counter means; first delay means responsive to each increment pulse for generating a write pulse a predetermined time following the occurrence of each increment pulse; means for generating decrement pulses; and second delay means responsive to each decrement pulse for decrementing said counter means a predetermined time following the occurrence of each decrement pulse.

Claim 6

An interrupt control system as defined in claim 4 wherein said predetermined time duration of said interrupt busy signal is longer than the time necessary to store or restore registor and/or flag data supplied from said central processing unit.

Claim 7

An interrupt control system as defined in claim 5 wherein at least one of said interrupt request signals is provided by a manual data entry system comprising: means for generating an interrupt request pulse in response to a manual command; a multiplicity of manually encodable switches; means for converting the encoded information into binary data; and means for generating an instruction for said central processing unit to read said data.