Error correcting circuits and methods for shift register type memories

Claim 2

A recirculating memory system comprising: a plurality of recirculating data paths in which sets of related data bits, one bit in each of the respective paths, are recirculated in synchronism; means coupled to the respective recirculating data paths to access a set of related bits in parallel; and a plurality of error detecting circuits, one for each recirculating data path and coupled to said accessing means to detect when the bits accessed from a given data path are a series of ones or a series of zeros.

Claim 3

A recirculating memory system according to claim 1 which further includes: a recirculating parity data path in parallel with said plurality of recirculating data paths and containing a series of parity bits one for each set of related data bits in said recirculating data paths; and parity checking means coupled to said accessing means and to said recirculating parity data path to check the parity of an accessed set of related data bits.

Claim 4

A recirculating memory system according to claim 1 wherein: said recirculating data paths are formed of MOS shift registers which are coupled together to form a plurality of recirculating loops.

Claim 5

A recirculating memory system according to claim 1 wherein: said recirculating data paths are formed of charge coupled devices.

Claim 6

A recirculating memory system according to claim 1 wherein: said recirculating data paths are formed in a magnetic medium having a magnetic bias to sustain single domain walls as individual data bits.

Claim 7

A recirculating memory system according to claim 1 further including: complementing means coupled to said accessing means to complement a given bit accessed from a recirculating data path when a corresponding error detecting circuit detects a series of ones or a series of zeros having been accessed from that data path.

Claim 8

In a recirculating memory system having a plurality of recirculating data paths wherein sets of related data bits, one from each data path, are recirculated in synchronism, accessing means coupled to each of said recirculating data paths to access a set of related data bits in parallel and a plurality of error detecting circuits coupled to respective ones of said recirculating data paths to detect whenever a given data path produces either a series on ones or a series of zeros upon successive accessing, the method comprising: reading a set of related data bits from said recirculating data paths into said accessing means; accessing additional sets of related data bits in sequence until the end of a block of said sets of related data bits; detecting if any of said error detecting circuits denotes a series of ones or a series of zeros having been read from corresponding recirculating data path; and transmitting said sets of related data bits from said accessing means.

Claim 9

In a recirculating memory system having a plurality of recirculating data paths wherein sets of related data bits, one from each data path, are recirculated in synchronism, accessing means coupled to each of said recirculating data paths to access a set of related data bits in parallel and a plurality of error detecting circuits coupled to respective ones of said recirculating data paths to detect whenever a given data path produces either a series on ones or a series of zeros upon successive accessing, the method comprising: reading a set of related data bits from said recirculating data paths into said accessing means; accessing additional sets of related data bits in sequence until the end of a block of said sets of related data bits; detecting if any of said error detecting circuits denotes a series of ones or a series of zeros having been read from corresponding recirculating data path; and transmitting said sets of related data bits from said accessing means.

Claim 10

A method according to claim 7 further including: complementing the respective bit corresponding to the data path where an error has been noted before the transmission of data from said accessing means.

Claim 11

A method according to claim 8 further including: setting the respective error detecting circuits to a no error condition prior to the beginning of accessing of said memory system.