Patent US3315492A successfully refreshed from Google Patents.
US4056711A
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Method and apparatus for programming microprocessors
Assignee: Individual
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Filing: 1975-10-24
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Granted: 1977-11-01
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Expires: 1995-10-24
Abstract
Abstract A method and apparatus for programming microprocessors which require machine code program instructions wherein black and white code strips are selectively pasted on a sequential instruction frame along a preprinted address code column, each code strip including a parallel trailer wherein the english equivalent of the instruction is displayed. A photoelecric, parallel reader is mounted on the frame for translation across the frame to sequentially load both the address code and the pasted on binary coded instructions into a static random access memory chip for the microprocessor. The technique thus provides for selective alteration of such program sequences by removing selected instruction strips and replacing such strips with other coded strips as required to modify the routine.
Inventors
- 👤 William Paul Lamar
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:07
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/10; G06K7/14; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/12; G05B19/124; G06F; G06F9/00; G06F9/06; G06F9/22; G06F9/24; G06K19/00; G06K19/04; G09; G09G; G09G2360/00; G09G2360/14; G09G2360/144
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
108 words
Apparatus for loading a sequence of instructions into a memory section of a data processing device comprising: a frame; address means selectively securable to said frame for providing a plurality of address signals indicative of the selected individual segments of said memory section; data means individually and selectively securable to said frame for providing a plurality of data signals in predetermined geometric relationship with selected ones of said address signals, and for providing a visual display indicative of said data signals; and reading means adapted for translation along said frame for responding to said address and data signal and providing coding signals indicative thereof to said memory section.
Claim 2
Dependent Claim
108 words
Apparatus for loading a sequence of instructions into a memory section of a data processing device comprising: a frame; address means selectively securable to said frame for providing a plurality of address signals indicative of the selected individual segments of said memory section; data means individually and selectively securable to said frame for providing a plurality of data signals in predetermined geometric relationship with selected ones of said address signals, and for providing a visual display indicative of said data signals; and reading means adapted for translation along said frame for responding to said address and data signal and providing coding signals indicative thereof to said memory section.
Claim 3
Dependent Claim
88 words
Apparatus according to claim 1 wherein: said frame includes a plate member; said address means comprises a first medium adapted for releasable attaachment to a selected first portion of said plate member in alignment subjacent to a predetermined one segment of said reading means; and said data means comprises a plurality of second medium elements each adapted for releasable attachment to selected second portions of said plate member, in a correlated alignment with selected sections of said medium and subjacent a predetermined other segment of said reading means.
Claim 4
Dependent Claim
31 words
Apparatus according to claim 2 wherein: said memory section comprises a static random access memory; said first medium includes a thin membrane; and said second medium elements include thin membrane strips.
Claim 5
Dependent Claim
30 words
Apparatus according to claim 3 wherein: said address means further includes a gating and a strobe signal associated with each said address signal for controlling said static random access memory.
Claim 6
Dependent Claim
45 words
Apparatus according to claim 4 wherein: said gating, strobe, address and data signals each comprise dark and light cells; and said reading means includes an array of photoelectric transducers disposed to provide said coding signals according to the distribution of said dark and white cells.
Claim 7
Dependent Claim
53 words
Apparatus according to claim 5 wherein: said address signals are arranged on said medium in a column of progressively increasing address codes, each said address codes having associated therewith an individual one of said gating and strobe signals; and individual ones of said strips are aligned in predetermined relationship with said address codes.
Claim 8
Dependent Claim
27 words
Apparatus according to claim 6 wherein: said dark and light cells on said medium and strips are arranged in columns subjacent selected ones of said photoelectric transducers.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-31 | 1981-05-02 | 1981-11-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-31 | 1985-05-02 | 1985-11-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-31 | 1989-05-02 | 1989-11-01 | $7700.00 | Window Closed / Lapsed |