Patent US3993055A successfully refreshed from Google Patents.
US4054747A
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Data buffer
Assignee: AG Communication Systems Corp
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Filing: 1976-05-20
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Granted: 1977-10-18
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Expires: 1996-05-20
Abstract
Abstract A data buffer makes use of a plurality of buffer storage cells into which serial bit streams are sequentially written, in order to obtain correction for phase jitter. A write clock signal is derived from the serial bit stream and is used to sequentially write the digits into the cells. A stable clock source is used to provide the basic timing for sequentially reading the bits out from the buffer storage cells, and a logic circuit is used in conjunction therewith to obtain the retimed serial bit stream. The write and read timing signals should have a maximum time separation to allow for maximum correction of phase jitter, and it is critical that the write and read signals should alternate. A monitor and reset circuit compares a selected write signal with a selected read signal and, where a violation of the alternating write-read condition occurs, the circuit resets the write timing and holds it until the read timing has attained a particular state.
Inventors
- 👤 Alvin L. Pachynski, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:54
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
200 words
Apparatus for retiming a serial bit stream which comprises: a first timing means providing N sequentially timed outputs, each at a rate which is 1/N th that of the bit rate of said serial bit stream, means for sequentially storing N binary digits, each said digit being written into said storing means by one of said N timed outputs from the first timing means; a second timing means including a clock means having an output which provides a clock rate at substantially the bit rate of said serial bit stream and having N sequentially timed outputs, each at a rate which is 1/N th of said clock rate; logic means responsive to said second timing means for sequentially reading out the binary digits from said storage means; and monitoring means having one input connected to monitor one of the N sequential timed outputs of said first timing means, having second and third inputs connected to monitor two of the N timed outputs of said second timing means to determine if the write-read inputs alternate and to provide an output signal which resets the N sequential outputs of one said timing means in the event the write-read sequence does not alternate.
Claim 2
Dependent Claim
200 words
Apparatus for retiming a serial bit stream which comprises: a first timing means providing N sequentially timed outputs, each at a rate which is 1/N th that of the bit rate of said serial bit stream, means for sequentially storing N binary digits, each said digit being written into said storing means by one of said N timed outputs from the first timing means; a second timing means including a clock means having an output which provides a clock rate at substantially the bit rate of said serial bit stream and having N sequentially timed outputs, each at a rate which is 1/N th of said clock rate; logic means responsive to said second timing means for sequentially reading out the binary digits from said storage means; and monitoring means having one input connected to monitor one of the N sequential timed outputs of said first timing means, having second and third inputs connected to monitor two of the N timed outputs of said second timing means to determine if the write-read inputs alternate and to provide an output signal which resets the N sequential outputs of one said timing means in the event the write-read sequence does not alternate.
Claim 3
Dependent Claim
79 words
Apparatus in accordance with claim 1 wherein said first timing means further comprises: a second clock means having a clock pulse repetition rate which is equal to the bit rate of the incoming bit stream and providing a clock pulse output at said rate; and a first counting means having an input connected to the output of said second clock means, said counting means providing N outputs, each providing a timing signal at 1/N th of the bit rate.
Claim 4
Dependent Claim
53 words
Apparatus in accordance with claim 2 wherein said sequential storing means further comprises: N memory cells, each having two inputs and an output, one said input of each cell being connected to receive said bit stream and the second input being connected to one of said N outputs of said first counting means.
Claim 5
Dependent Claim
68 words
Apparatus in accordance with claim 3 wherein said second timing means further comprises: a stable master clock having a clock pulse repetition rate which is equal to that of said second clock means; and a second counting means having an input connected to the output of said master clock, said counting means having N outputs, each providing a timing signal at 1/N th of the master clock rate.
Claim 6
Dependent Claim
101 words
Apparatus in accordance with claim 4 wherein said logic means further comprises: N and-gates, each having two inputs and an output, one said input being connected to one said output of one said memory cell, and the second said output being connected to one of said N outputs of said second counting means; an OR-gate having N inputs and an output, each input being connected to one said AND-gate output; and retiming means having one input connected to the output of said OR-gate and a second input connected to the output of said master clock whereby the bit stream is retimed.
Claim 7
Dependent Claim
54 words
Apparatus in accordance with claim 5 wherein said monitoring means further comprises: means for comparing a selected output from said first counting means with a selected output from said second counting means to determine if there is an alternating sequence; and means for resetting said first counting means when said alternating sequence is violated.
Claim 8
Dependent Claim
66 words
In a data buffer for retiming a serial bit stream, monitor and reset apparatus which comprises: a first counting means; a second counting means; means for comparing a selected output of said first counting means with a selected output of said second counting means to determine if there is an alternating sequence; and means for resetting said first counting means when said alternating sequence is violated.
Claim 9
Dependent Claim
66 words
In a data buffer for retiming a serial bit stream, monitor and reset apparatus which comprises: a first counting means; a second counting means; means for comparing a selected output of said first counting means with a selected output of said second counting means to determine if there is an alternating sequence; and means for resetting said first counting means when said alternating sequence is violated.
Claim 10
Dependent Claim
93 words
Monitor and reset apparatus in accordance with claim 7 wherein said comparing means further comprises: a first flip-flop having a reset input connected to receive the selected output of said first counting means; inverting means having an input connected to receive the selected output from said second counting means and having an output connected to the set input of the first flip-flop; the output of said flip-flop being of one state when the selected outputs from said first and second counting means alternate and of the other state when they do not alternate.
Claim 11
Dependent Claim
111 words
Monitor and reset apparatus in accordance with claim 8 wherein said means responsive further comprises: logic means having as one input the selected output from said first counting means, as a second input the selected inverted output from said second counting means, as a third input the output of said first flip-flop, and as a fourth input a second selected output from said second counting means; said logic means providing two outputs which are both of one like state when the first and second inputs occur alternately and are of opposite states otherwise; and gating means responsive to the opposite states of said logic means to reset said first counting means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-17 | 1981-04-18 | 1981-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-17 | 1985-04-18 | 1985-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-17 | 1989-04-18 | 1989-10-18 | $7700.00 | Window Closed / Lapsed |