US4052705A
Expired / Lapsed
US
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Memory device for two-dimensional radiant energy array computers
Assignee: National Aeronautics and Space Administration
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Filing: 1976-02-13
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Granted: 1977-10-04
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Expires: 1996-02-13
Abstract
Abstract Memory device for two-dimensional radiant energy array computers in which the memory device stores digital information in an input array of radiant energy digital signals that are characterized by ordered rows and columns. The memory device includes a radiant energy logic storing device having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array and a regenerative feedback device that couples one of the input surface locations to the output surface location in a manner for causing regenerative feedback.
Inventors
- 👤 David H. Schaefer
- 👤 James P. Strong, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:02
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/42; G02; G02F; G02F3/00; G11C13/00; G11C13/04; G11C13/047; H; H03; H03K; H03K19/00; H03K19/02; H03K19/14; H03K3/00; H03K3/02; H03K3/42
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
81 words
A memory device for storing the digital information in an input array of radiant energy digital signals characterized by ordered rows and columns comprising: radiant energy logic means having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array; means for coupling one of said input surface locations to said output surface location in a manner for causing regenerative feedback.
Claim 2
Dependent Claim
81 words
A memory device for storing the digital information in an input array of radiant energy digital signals characterized by ordered rows and columns comprising: radiant energy logic means having a pair of input surface locations for receiving a pair of separate radiant energy digital signal arrays and an output surface location adapted to transmit a radiant energy digital signal array; means for coupling one of said input surface locations to said output surface location in a manner for causing regenerative feedback.
Claim 3
Dependent Claim
28 words
The device of claim 1 in combination with a clock radiant energy array signal source and wherein said coupling means includes gating means responsive to said clock source.
Claim 4
Dependent Claim
27 words
The device of claim 1 in combination with an erase radiant energy array source and wherein said coupling means includes gating means responsive to said erase source.
Claim 5
Dependent Claim
50 words
The memory device of claim 1 including another of said input surface locations responsive to one of said pairs of input digital radiant energy arrays and a store radiant energy array input which indicates which elements of said one of said radiant energy arrays becomes stored in said memory device.
Claim 6
Dependent Claim
63 words
The memory device of claim 4 including gating means connected between said another of said input surface locations and said one of said input surface locations for transmitting to said one of said input locations only elements of said one of said radiant energy arrays which are in corresponding row and column positions to digital one elements of said store radiant energy array.
Claim 7
Dependent Claim
15 words
The memory device of claim 5 wherein said gating means is an AND logic device.
Claim 8
Dependent Claim
23 words
The memory device of claim 1 including gating means connected between said one of said input surface locations and said output surface location.
Claim 9
Dependent Claim
15 words
The memory device of claim 7 wherein said gating means is an OR logic device.
Claim 10
Dependent Claim
15 words
The memory device of claim 3 wherein said gating means is and AND logic device.
Claim 11
Dependent Claim
49 words
The memory device of claim 3 wherein said coupling means further includes a combining means connected to said AND logic device and being responsive to said erase source and said regenerative feedback, for combining said erase source and said regenerative feedback prior to gating by said AND logic device.
Claim 12
Dependent Claim
21 words
The memory device of claim 10 wherein said AND logic device is connected to said one of said input surface locations.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-03 | 1981-04-04 | 1981-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-03 | 1985-04-04 | 1985-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-03 | 1989-04-04 | 1989-10-04 | $7700.00 | Window Closed / Lapsed |