Apparatus and method for diagnosing digital data devices

Claim 2

In a digital data processing device, apparatus for diagnosing functional hardware errors in certain logic signals produced therein, comprising: a. counter means for counting a predetermined test step sequence and producing binary output signals indicative of such steps; b. memory means for storing predetermined code words indicative of diagnostic data at addressable storage locations therein; and c. address generating means coupled to receive said binary output signals from said counter means and said certain logic signals for generating an address utilized by said memory means for accessing said predetermined code words.

Claim 3

An apparatus as in claim 1 wherein the memory is a read only memory.

Claim 4

An apparatus as in claim 2 which further includes a means for holding the state of said certain logic signals, said means for holding being connected between said certain logic signals and said address generating means.

Claim 5

An apparatus as in claim 3 for use in said digital data processing device of the type having a program address counter, wherein said means for counting comprises a counter independent from said program address counter.

Claim 6

An apparatus as in claim 3 wherein the means for holding comprises a register having a bit position for each of the said certain logic signals.

Claim 7

An apparatus as in claim 3 wherein said predetermined code words comprise a single bit indicating whether an error is present in said digital data processing device.

Claim 8

An apparatus as in claim 3 for use in said digital data processing device of the type having a plurality of hardware modules, wherein said code words comprise a multibit code indicating whether an error is present in said digital data processing device and, if so, which hardware module is at fault.

Claim 9

An apparatus as in claim 7 which further includes a means responsive to said code word for indicating which said hardware module is at fault, said means for indicating connected to the output of said memory means.

Claim 10

In a computer of the type having a microprocessor for performing computations in accordance with a stored program of instructions, a microprogram address counter, and a plurality of hardware modules, an apparatus for diagnosing computer hardware errors among certain logic signals, comprising: a. means for counting a predetermined test step sequence; and b. a memory having a plurality of addressable storage locations containing a predetermined code in the storage locations representing appropriate diagnostic information, said memory being addressed by said means for counting and by said certain logic signals, and an output for reading the contents of the storage locations.

Claim 11

In a computer of the type having a microprocessor for performing computations in accordance with a stored program of instructions, a microprogram address counter, and a plurality of hardware modules, an apparatus for diagnosing computer hardware errors among certain logic signals, comprising: a. means for counting a predetermined test step sequence; and b. a memory having a plurality of addressable storage locations containing a predetermined code in the storage locations representing appropriate diagnostic information, said memory being addressed by said means for counting and by said certain logic signals, and an output for reading the contents of the storage locations.

Claim 12

An apparatus as in claim 9 wherein said memory is a read only memory.

Claim 13

An apparatus as in claim 10 which further includes a means for holding the state of said certain logic signals, said means for holding being connected between said certain logic signals and said address generating means.

Claim 14

An apparatus as in claim 11 wherein said means for counting is the microprogram address counter.

Claim 15

An apparatus as in claim 11 wherein said means for counting comprises a counter independent from the microprogram address counter.

Claim 16

An apparatus as in claim 11 wherein said test steps are microinstruction executions and said test step sequence is a sequence of microinstruction executions.

Claim 17

An apparatus as in claim 14 wherein said certain logic signals include logic signals of said digital data devices which, if in error, would prevent microinstruction execution and sequencing.

Claim 18

In a computer of the type having a program address counter and a plurality of hardware modules, a method for diagnosing computer hardware errors among certain logic signals, comprising the steps of: a. performing a test step sequence by executing a known set of test step microinstructions in a sequential manner; b. counting each step in the test step sequence; c. holding the state of each of the certain logic signals at each step of the test step sequence; d. addressing a read only memory containing a code in the storage locations representing appropriate diagnostic information with both the count of the step in the test step sequence and with the state of the certain logic signals being held; e. reading the contents of the storage locations in the memory; and f. presenting the contents read for an external inspection.

Claim 19

In a computer of the type having a program address counter and a plurality of hardware modules, a method for diagnosing computer hardware errors among certain logic signals, comprising the steps of: a. performing a test step sequence by executing a known set of test step microinstructions in a sequential manner; b. counting each step in the test step sequence; c. holding the state of each of the certain logic signals at each step of the test step sequence; d. addressing a read only memory containing a code in the storage locations representing appropriate diagnostic information with both the count of the step in the test step sequence and with the state of the certain logic signals being held; e. reading the contents of the storage locations in the memory; and f. presenting the contents read for an external inspection.