US4020286A
Expired / Lapsed
US
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Signal analysis apparatus for amplitude statistics
Assignee: Metrosonics Inc
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Filing: 1975-05-19
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Granted: 1977-04-26
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Expires: 1995-05-19
Abstract
Abstract Acoustical signals of sound and noise levels are analyzed automatically for statistical characteristics of such signals which are required to be measured by recent environmental and health and safety regulations. The signals are applied to an analog to digital converter which tracks rapid changes in signal level and provides a digital output which represents the level in logarithmic (decibel) steps. The digital outputs which exist at successive sampling times provide a history of the sound level characteristics. A memory having a large sample capacity is provided to store these digital level samples. A storage capacity of several million samples is obtained by a random access memory which is addressed by the data representing the sound levels. A separate address is provided for each level (viz., for each of 100 levels differing from each other by 1 dB steps). Logic in the memory causes the digital numbers to be incremented each time a sample for the sound level corresponding to the address is presented to the memory. Totalizers and other arithmetic circuits receive data read out of the memory and provide outputs such as the percent of time that each sound level is exceeded, the amplitude distribution of the sound levels, the sound levels exceeded certain percentages of the time and other statistical amplitude distributions as are or may be required by environmental and health and safety regulations. Features of the invention include: an analog to digital converter with a variable gain amplifier whose feedback loop contains a BCD counter which generates the digital output signal; and an incremental adder which includes a counter for sequentially addressing each bit of stored digital numbers to be incremented.
Inventors
- 👤 Barry L. Ceci
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:19
CPC Classifications
G; G01; G01H; G01H3/00; G01H3/10; G01H3/12
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
247 words
A signal analysis system which can analyze the statistical characteristics of signals while they occur in real time, which system comprises a. means for converting in real time an input signal into first digital signals corresponding to the level of said input signal in a multiplicity of steps each representing a different successively higher value of the level of said signals, b. means operative in real time and responsive to said first digital signals for generating and storing second digital signals each corresponding to a different one of said first digital signals and representing the number of said first digital signals which correspond thereto occurring during a given period of time, c. means also operative in real time and responsive to said second digital signals for providing output signals representing statistical characteristics of said input signals, d. said generating and storing means including a random access memory, means responsive to said first digital signal for addressing said memory to the locations of storage of the second digital signals corresponding to said first digital signals, a serial adder, and means for serially recirculating data through said adder out of and back into said memory for incrementing said second digital signal, and e. said recirculating means including a counter for counting up to a count number at least equal to the number of bits in said second digital signal, said counter being connected to said random access memory for sequentially addressing each bit of said stored second digital signals.
Claim 2
Dependent Claim
247 words
A signal analysis system which can analyze the statistical characteristics of signals while they occur in real time, which system comprises a. means for converting in real time an input signal into first digital signals corresponding to the level of said input signal in a multiplicity of steps each representing a different successively higher value of the level of said signals, b. means operative in real time and responsive to said first digital signals for generating and storing second digital signals each corresponding to a different one of said first digital signals and representing the number of said first digital signals which correspond thereto occurring during a given period of time, c. means also operative in real time and responsive to said second digital signals for providing output signals representing statistical characteristics of said input signals, d. said generating and storing means including a random access memory, means responsive to said first digital signal for addressing said memory to the locations of storage of the second digital signals corresponding to said first digital signals, a serial adder, and means for serially recirculating data through said adder out of and back into said memory for incrementing said second digital signal, and e. said recirculating means including a counter for counting up to a count number at least equal to the number of bits in said second digital signal, said counter being connected to said random access memory for sequentially addressing each bit of said stored second digital signals.
Claim 3
Dependent Claim
60 words
The invention as set forth in claim 1 wherein said output signal providing means includes means for generating successively third digital signals corresponding to said addresses and for operating said counter to count up to said count number during each of said third digital signal, serial totalizer circuit means, said totalizer means being connected to the output of said memory.
Claim 4
Dependent Claim
171 words
A signal analysis system which can analyze the statistical characteristics of signals while they occur in real time which system comprises a. means for converting in real time an input signal into first digital signals corresponding to the level of said input signal in a multiplicity of steps each representing a different successively higher value of the level of said signals, b. means operative in real time and responsive to said first digital signals for generating and storing second digital signals each corresponding to a different one of said first digital signals and representing the number of said first digital signals which correspond thereto occurring during a given period of time, c. means also operative in real time responsive to said second digital signals for providing output signals representing statistical characteristics of said input signals, and d. said converting means being analog to digital converter means for continuously following variations in amplitude of said input signal, said analog to digital converter means having a counter for generating said first digital signals.
Claim 5
Dependent Claim
171 words
A signal analysis system which can analyze the statistical characteristics of signals while they occur in real time which system comprises a. means for converting in real time an input signal into first digital signals corresponding to the level of said input signal in a multiplicity of steps each representing a different successively higher value of the level of said signals, b. means operative in real time and responsive to said first digital signals for generating and storing second digital signals each corresponding to a different one of said first digital signals and representing the number of said first digital signals which correspond thereto occurring during a given period of time, c. means also operative in real time responsive to said second digital signals for providing output signals representing statistical characteristics of said input signals, and d. said converting means being analog to digital converter means for continuously following variations in amplitude of said input signal, said analog to digital converter means having a counter for generating said first digital signals.
Claim 6
Dependent Claim
44 words
The invention as set forth in claim 3 wherein said analog to digital converter also includes a variable gain amplifier, operated by said counter to change the gain thereof, and means responsive to the output of said amplifier for changing the count stored therein.
Claim 7
Dependent Claim
53 words
The invention as set forth in claim 4 wherein said count changing means includes comparator means for detecting when said amplifier output changes with respect to a certain output level and for providing pulses upon occurrence of said changes, and means for applying said pulses to said counter for changing the count therein.
Claim 8
Dependent Claim
49 words
The invention as set forth in claim 5 further comprising means for changing the amplitude of said amplifier output signal in opposite senses, and means responsive to said pulses for changing said amplitude in the sense opposite to the sense in which amplitude changes when said pulses are produced.
Claim 9
Dependent Claim
34 words
The invention as set forth in claim 6 wherein said amplitude changing means includes a capacitor connected to said amplifier, and circuit means responsive to said pulses for selectively charging and discharging said capacitor.
Claim 10
Dependent Claim
106 words
The invention as set forth in claim 6 wherein said variable gain amplifier includes a plurality of stages, each having networks connected thereto for controlling the gain of said amplifier logarithmically in binarily related steps to provide gain which varies in a multiplicity of dB steps, switching means connected to said networks for switching said networks into and out of said stages, means coupling said switching means to said counter, so as to change the count in said counter and varying the gain of said amplifier to maintain the output thereof at a certain amplitude whereby the count in said counter provides said first digital signal.
Claim 11
Dependent Claim
54 words
The invention as set forth in claim 8 wherein said variable gain amplifier includes, and has connected to the output of the last stage thereof, means for providing as said amplifier output signal a signal corresponding to the root means square of the average value (RMS-Average) of the signal produced by said last stage.
Claim 12
Dependent Claim
92 words
The invention as set forth in claim 9 wherein said RMS average value producing means comprises a first stage for rectifying last stage output, a first log amplifier, a summing amplifier for providing a signal corresponding to the inverse log of the sum of the signals applied thereto, a low pass filter circuit input connected to the output of said summing amplifier for providing said amplifier output signal, another log amplifier to which said filter is output connected, said summing amplifier being input connected to said first and said other log amplifier.
Claim 13
Dependent Claim
72 words
The invention as set forth in claim 10 wherein said filter circuit includes a capacitor connected to the output thereof and means for charging and discharging said capacitor when said count in said counter changes respectively to change the amplifier output in a sense opposite to changes in the gain of said amplifier whereby said change in gain can rapidly track said input signal so as to maintain said amplifier output constant.
Claim 14
Dependent Claim
149 words
An analog to digital converter which comprises a variable gain amplifier responsive to the analog input signal to be digitized, a counter for controlling the gain of said amplifier, and providing a digital signal corresponding to the amplitude of said input signal, a comparator responsive to a reference voltage and the output of said amplifier for providing output pulses when said output increases or decreases by certain amplitudes with respect to said reference voltage, means for applying said pulses to said counter for increasing and decreasing the count stored therein to maintain said amplifier output within a range between said certain amplitudes, and means responsive to said pulses for changing said output by approximately said certain amplitude in senses opposite to the sense in which said output changed when said pulses were produced so as to enable said converter rapidly to track changes in amplitude of said input signal.
Claim 15
Dependent Claim
149 words
An analog to digital converter which comprises a variable gain amplifier responsive to the analog input signal to be digitized, a counter for controlling the gain of said amplifier, and providing a digital signal corresponding to the amplitude of said input signal, a comparator responsive to a reference voltage and the output of said amplifier for providing output pulses when said output increases or decreases by certain amplitudes with respect to said reference voltage, means for applying said pulses to said counter for increasing and decreasing the count stored therein to maintain said amplifier output within a range between said certain amplitudes, and means responsive to said pulses for changing said output by approximately said certain amplitude in senses opposite to the sense in which said output changed when said pulses were produced so as to enable said converter rapidly to track changes in amplitude of said input signal.
Claim 16
Dependent Claim
34 words
The invention as set forth in claim 12 wherein said amplifier output changing means includes a capacitive circuit in said amplifier and means responsive to said pulses for charging and discharging said capacitive circuit.
Claim 17
Dependent Claim
85 words
The invention as set forth in claim 13 wherein said amplifier includes circuit means at the output thereof for providing, as said amplifier output, a signal corresponding to the root means square of the average value of the amplitude of an input signal to said circuit means, said circuit means including a low pass filter including said capacitive circuit, and switching means operated by said pulses for connecting sources of voltage of opposite polarity to said capacitive circuit for charging and discharging said capacitive circuit.
Claim 18
Dependent Claim
129 words
The invention as set forth in claim 12 wherein said variable gain amplifier includes a plurality of tandem stages providing gains in a multiplicity of binarily and logarithmically related dB steps, switching means in said stages coupled to said counter for changing the gain of said amplifier to correspond inversely to the count stored in said counter, said counter being an up/down counter having up and down inputs, and said means for applying said pulses to said counter including steering means for applying a pulse to the up input of said counter when said output increases and to said down input of said counter when said gain decreases whereby the count in said counter is the digital signal which represents the amplitude of said input signal in dB steps.
Claim 19
Dependent Claim
15 words
The invention as set forth in claim 15 wherein said counter is a BCD counter.
Claim 20
Dependent Claim
64 words
The invention as set forth in claim 16 wherein said amplifier stages are each operational amplifiers having an input network and an output network each including a separate switch of said switching means for respectively increasing and decreasing the gain of said each stage when said switches are enabled, and logic means including a nine's complementor for coupling said BCD counter to said switches.
Claim 21
Dependent Claim
46 words
The invention as set forth in claim 17 wherein said stages are A.C. coupled to each other, and circuit means connected to the last of said stages for converting the output of said last stage into a dc signal corresponding to the root means square thereof.
Claim 22
Dependent Claim
261 words
A memory system for storing data corresponding to the presence of a multiplicity of different input words of digital data, which system comprises a random access memory (RAM) having address inputs greater in number than the number of bits in said input words, data inputs and outputs and a write command input, means for presenting said input words to part of said address inputs, so as to select certain bit storage locations in said RAM corresponding thereto, a counter having a plurality of outputs corresponding in number to the remaining part of said address inputs and having a count capacity at least equal to the number of bits in each said storage locations for addressing each said locations, a serial adder having a pair of inputs and a sum output, said RAM data output being connected to one of said serial adder inputs, means for applying an input pulse to the other of said serial adder sum inputs when said counter reaches a certain count, and means for simultaneously enabling said RAM write input to receive a write command and said RAM data input to receive the sum output of said adder for a period of time commencing when said data representing the presence of said input word is to be written in said memory and said counter reaches a count greater by at least said number of bit storage locations than said certain count whereby to increment the value of an output digital word stored in the RAM bit storage locations corresponding thereto when said input digital word is present.
Claim 23
Dependent Claim
261 words
A memory system for storing data corresponding to the presence of a multiplicity of different input words of digital data, which system comprises a random access memory (RAM) having address inputs greater in number than the number of bits in said input words, data inputs and outputs and a write command input, means for presenting said input words to part of said address inputs, so as to select certain bit storage locations in said RAM corresponding thereto, a counter having a plurality of outputs corresponding in number to the remaining part of said address inputs and having a count capacity at least equal to the number of bits in each said storage locations for addressing each said locations, a serial adder having a pair of inputs and a sum output, said RAM data output being connected to one of said serial adder inputs, means for applying an input pulse to the other of said serial adder sum inputs when said counter reaches a certain count, and means for simultaneously enabling said RAM write input to receive a write command and said RAM data input to receive the sum output of said adder for a period of time commencing when said data representing the presence of said input word is to be written in said memory and said counter reaches a count greater by at least said number of bit storage locations than said certain count whereby to increment the value of an output digital word stored in the RAM bit storage locations corresponding thereto when said input digital word is present.
Claim 24
Dependent Claim
57 words
The invention as set forth in claim 19 including a pair of said RAMS having said counter and serial adder connected in parallel thereto, and means responsive to the highest order bit of said input digital word to enable different ones of said pair of RAMS to receive said input digital words at the address inputs thereof.
Claim 25
Dependent Claim
40 words
The invention as set forth in claim 19 including a counter for generating said input digital words, and means for incrementing said counter while said simultaneous write and data input enabling means are inhibited for serially reading out said RAM.
Claim 26
Dependent Claim
164 words
An analog to digital converter which comprises a. a variable gain amplifier responsive to the analog input signal to be digitized, said amplifier having a plurality of networks each providing said amplifier with a different gain, said different gains being related to each other in successively higher steps, and switching means connected to said networks for selectively changing the gain of said amplifier, b. a counter having an input and a plurality of outputs providing a digital signal representing the count therein and the level of said analog input signal, means coupling said outputs to said switching means for changing the gain of said amplifier in accordance with the value of said digital signal, and c. a comparator responsive to a reference voltage having an upper and lower values and to the output of said amplifier for providing output pulses to the input of said counter for increasing and decreasing the count therein to maintain said amplifier output between said upper and lower values.
Claim 27
Dependent Claim
164 words
An analog to digital converter which comprises a. a variable gain amplifier responsive to the analog input signal to be digitized, said amplifier having a plurality of networks each providing said amplifier with a different gain, said different gains being related to each other in successively higher steps, and switching means connected to said networks for selectively changing the gain of said amplifier, b. a counter having an input and a plurality of outputs providing a digital signal representing the count therein and the level of said analog input signal, means coupling said outputs to said switching means for changing the gain of said amplifier in accordance with the value of said digital signal, and c. a comparator responsive to a reference voltage having an upper and lower values and to the output of said amplifier for providing output pulses to the input of said counter for increasing and decreasing the count therein to maintain said amplifier output between said upper and lower values.
Claim 28
Dependent Claim
44 words
The invention as set forth in claim 22 further comprising circuit means connected between said amplifier output and said comparator for converting said amplifier output into a signal corresponding to the RMS of the average value thereof and applying said signal to said comparator.
Claim 29
Dependent Claim
33 words
The invention as set forth in claim 22 wherein said amplifier has a plurality of operational amplifier stages, each including a different one of said networks respectively in input and feedback relationship therewith.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-25 | 1980-10-25 | 1981-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-25 | 1984-10-25 | 1985-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-25 | 1988-10-25 | 1989-04-26 | $7700.00 | Window Closed / Lapsed |