Central supervisory and control system generating 16-bit output

Claim 2

A communication system wherein a central processing means and a plurality of remote stations transmit and receive messages to and from each other over a common transmission channel, said messages constructed of a plurality of bits, said system comprising: central processing means having processing means and universal asynchronous receiver transmitter means comprising, bit means for generating a plurality of bit signals each corresponding to a bit of a message received from said plurality of remote stations, error means for generating an error signal having a state dependent upon whether there is an error in the transmission of messages from said plurality of remote stations, and busy means for generating a busy signal having a state dependent upon whether the universal asynchronous receiver transmitter means is busy; said central processing means further comprising, bit output means connected to receive such bit signals for generating bit outputs, error output means connected to receive said error signal for generating an error output, busy output means connected to receive said busy signal for generating a busy output, and no response means responsive to said messages from said remote states for generating a no response signal having a state dependent upon whether or not a message is received from a remote station within a predetermined time; said processing means for receiving substantially simultaneously said bit outputs, error output, busy output and no response output for reading said outputs in one operation; transmission channel means connected to said central processing means; and a plurality of remote stations each connected to said transmission channel means for receiving and transmitting messages.

Claim 3

The system of claim 1 wherein said bit output means comprises a plurality of latches for receiving said bit signals and for generating said bit outputs.

Claim 4

The system of claim 2 wherein said bit means comprises a serial shift register for receiving said messages and clock means for shifting said bits in said message through said serial shift register, said serial shift register having a plurality of outputs for providing said bit signals.

Claim 5

The system of claim 3 wherein said error output means comprises a latch for receiving said error signal and for generating said error output.

Claim 6

The system of claim 4 wherein each transmission of a message comprises a first half and a second half and wherein said error means comprises comparator means for comparing the first half of said transmission to said second half of said transmission bit by bit and generating said error signal having a state dependent upon whether corresponding bits of said first half and said second half of said transmission fail to match.

Claim 7

The system of claim 5 wherein said busy output means comprises a latch for receiving said busy signal and for generating said busy output.

Claim 8

The system of claim 6 wherein said busy means comprises a transmit flip-flop for generating said busy signal when said universal asynchronous receiver transmitter means is busy transmitting messages.

Claim 9

The system of claim 7 wherein said universal asynchronous receiver transmitter means further comprises send complete means for generating a send complete signal when said universal asynchronous receiver transmitter means has completed transmitting messages, receive complete means for generating a receive complete signal when said universal asynchronous receiver transmitter means has completed receiving messages, and said no response means comprises timer latch means responsive to said send complete and receive complete signals for generating said no response signal having a state dependent upon whether or not a message is received from a remote station within a predetermined time.

Claim 10

The system of claim 8 wherein said universal asynchronous receiver transmitter means further comprises means responsive to said processing means for substantially simultaneously enabling said latches of said bit output means, error output means, busy output means and said timer latch means for simultaneously generating said bit outputs, error outputs, busy outputs, and no response outputs.

Claim 11

A communication system wherein a central processing means and a plurality of remote stations transmit and receive messages to and from each other over a common transmission channel, said messages constructed of a plurality of bits, said system comprising: a plurality of remote stations for generating messages containing bits of information in response to messages transmitted by said central processing means; transmission channel means connected to said plurality of remote station means for conducting said messages; and, central processing means comprising processing means and universal asynchronous receiver transmitter system means connected to said transmission channel means for receiving said messages containing bits of information and for substantially simultaneously generating bit outputs representing said information, an error output having a state dependent upon whether an error in transmission has occurred, a busy output having a state dependent upon whether the universal asynchronous receiver transmitter system means is busy and a no response output having a state dependent upon whether or not a message is received from a remote station within a predetermined time, said outputs for use by said processing means.

Claim 12

A communication system wherein a central processing means and a plurality of remote stations transmit and receive messages to and from each other over a common transmission channel, said messages constructed of a plurality of bits, said system comprising: a plurality of remote stations for generating messages containing bits of information in response to messages transmitted by said central processing means; transmission channel means connected to said plurality of remote station means for conducting said messages; and, central processing means comprising processing means and universal asynchronous receiver transmitter system means connected to said transmission channel means for receiving said messages containing bits of information and for substantially simultaneously generating bit outputs representing said information, an error output having a state dependent upon whether an error in transmission has occurred, a busy output having a state dependent upon whether the universal asynchronous receiver transmitter system means is busy and a no response output having a state dependent upon whether or not a message is received from a remote station within a predetermined time, said outputs for use by said processing means.

Claim 13

The system of claim 10 wherein said universal asynchronous receiver transmitter system means comprises a shift register for receiving said messages comprising said bits of information, clock means for shifting said bits through said shift register and a plurality of outputs for providing said bit outputs.

Claim 14

The system of claim 11 wherein said messages containing bits of information are transmitted in first and second halves of a transmission, and wherein said universal asynchronous receiver transmitter system means comprises comparator means for comparing said first half of said transmission to said second half of said transmission, bit by bit, and providing said error output having a state dependent upon whether two corresponding bits in said first and second halves of said transmission fail to match.

Claim 15

The system of claim 12 wherein said universal asynchronous receiver transmitter means comprises means for shifting said first half of said transmission into said shift register and for shifting said first half of said transmission out of said shift register to said comparator, and for simultaneously presenting said second half of said transmission to said comparator and for shifting said second half of said transmission into said shift register.

Claim 16

The system of claim 12 wherein said universal asynchronous receiver transmitter means comprises transmit flip-flop means for generating said busy output having a state dependent upon whether said universal asynchronous receiver transmitter system means is busy transmitting messages.

Claim 17

A communication system wherein a central processing means and a plurality of remote stations transmit and receive messages to and from each other over a common transmission channel, said messages constructed of a plurality of bits, and wherein said messages are transmitted once during a first half of a transmission and a second time during a second half of said transmission by said central processing means and said plurality of remote stations for error checking, a universal asynchronous receiver transmitter for each said central processing means and said plurality of remote stations comprising: shift register means for storing said messages received or to be transmitted over said transmission channels; clock and mode control means for determining whether said universal asynchronous receiver transmitter is in a transmitting mode or a receiving mode for shifting said message during said first half of said transmission and then said message during said second half of said transmission through said shift register during said receiving mode and for shifting said message onto said transmission channel during said first half of said transmission and back into said shift register for said second half of said transmission during said transmitting mode; and, error checking means responsive to said clock and mode control means during said receiving mode for receiving said message received by said shift register during said first half of said transmission out of said shift register and said message during said second half of said transmission as it is being shifted into said shift register means and for comparing bit by bit said first half of said transmission to said second half of said transmission for producing an error signal having a state dependent upon whether any two corresponding bits fail to match.

Claim 18

A communication system wherein a central processing means and a plurality of remote stations transmit and receive messages to and from each other over a common transmission channel, said messages constructed of a plurality of bits, and wherein said messages are transmitted once during a first half of a transmission and a second time during a second half of said transmission by said central processing means and said plurality of remote stations for error checking, a universal asynchronous receiver transmitter for each said central processing means and said plurality of remote stations comprising: shift register means for storing said messages received or to be transmitted over said transmission channels; clock and mode control means for determining whether said universal asynchronous receiver transmitter is in a transmitting mode or a receiving mode for shifting said message during said first half of said transmission and then said message during said second half of said transmission through said shift register during said receiving mode and for shifting said message onto said transmission channel during said first half of said transmission and back into said shift register for said second half of said transmission during said transmitting mode; and, error checking means responsive to said clock and mode control means during said receiving mode for receiving said message received by said shift register during said first half of said transmission out of said shift register and said message during said second half of said transmission as it is being shifted into said shift register means and for comparing bit by bit said first half of said transmission to said second half of said transmission for producing an error signal having a state dependent upon whether any two corresponding bits fail to match.

Claim 19

The system of claim 15 wherein said clock and mode control means comprises a three phase clock driven by a master clock and connected to said shift register means for shifting said bits into and out of said shift register means and a count of 15 counter for generating first and second count of 15 signals and means responsive to said second count of 15 signals for terminating said transmitting and receiving modes.

Claim 20

The system of claim 16 wherein said clock and mode control means comprises transmit flip-flop means responsive to a transmit signal for resetting said three phase clock and said count of 15 counter to initiate said transmitting mode and said receiving mode and for generating a busy signal during said transmitting mode.

Claim 21

The system of claim 17 wherein said shift register means comprises outputs for presenting said bits of said messages received during said receiving mode, and inputs and load means for loading into said shift register bits of said messages to be transmitted during said transmitting mode.

Claim 22

The system of claim 18 wherein said clock and mode control means comprises means for generating a receive complete signal at said second count of 15 from said count of 15 counter at the end of said receiving mode if no error between said first and second halves of said transmissions has occurred.

Claim 23

The system of claim 19 wherein said clock and mode control means comprises means for generating a send complete signal at said second count of 15 from said count of 15 counter at the end of said transmitting mode.