US4002984A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for determining the time duration of received oscillations
Assignee: Deutsche Thomson OHG
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Filing: 1975-11-26
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Granted: 1977-01-11
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Expires: 1995-11-26
Abstract
Abstract A circuit arrangement for evaluating received oscillations whose maximum possible time duration is predetermined, by determining the time duration of the oscillations. Pulses of a constant frequency are fed to a counter during the time the oscillations are being received and a count representative of the number of counted pulses is stored in a memory as information. Whenever the counter state representing the maximum possible time duration has been exceeded, indicating that the received oscillations are interfering oscillations or noise, the feeding of pulses to the counter is interrupted and the stored information is erased.
Inventors
- 👤 Wiilf-Christian Streckenbach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:56
CPC Classifications
H; H03; H03J; H03J9/00; H03J9/04; H04; H04B; H04B11/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
165 words
In a circuit arrangement for evaluating a received signal of a predetermined frequency, and whose maximum possible time duration is predetermined, by determining the time duration of the signal of said predetermined frequency, said circuit arrangement including a counter, means responsive to said received signal for feeding pulses of a constant frequency to the counting input of said counter to cause same to count during the time said signal of predetermined frequency is being received, and a memory means having its input connected to an output of said counter for storing a count representative of the number of counted pulses, the improvement comprising logic means, responsive to the counting state of said counter, for interrupting the feeding of said pulses to said input of said counter and for erasing the information stored in said memory whenever a counter state corresponding to said maximum permissible time duration has been exceeded due to receipt of interference signals having said predetermined frequency, whereby an erroneous evaluation is avoided.
Claim 2
Dependent Claim
165 words
In a circuit arrangement for evaluating a received signal of a predetermined frequency, and whose maximum possible time duration is predetermined, by determining the time duration of the signal of said predetermined frequency, said circuit arrangement including a counter, means responsive to said received signal for feeding pulses of a constant frequency to the counting input of said counter to cause same to count during the time said signal of predetermined frequency is being received, and a memory means having its input connected to an output of said counter for storing a count representative of the number of counted pulses, the improvement comprising logic means, responsive to the counting state of said counter, for interrupting the feeding of said pulses to said input of said counter and for erasing the information stored in said memory whenever a counter state corresponding to said maximum permissible time duration has been exceeded due to receipt of interference signals having said predetermined frequency, whereby an erroneous evaluation is avoided.
Claim 3
Dependent Claim
15 words
A circuit arrangement as defined in claim 1 wherein said memory is a forward-backward counter.
Claim 4
Dependent Claim
29 words
A circuit arrangement as defined in claim 1 wherein the number of pulses fed to said counter is equal to the number of received oscillations of said predetermined frequency.
Claim 5
Dependent Claim
73 words
An ultrasonic remote control apparatus including a circuit arrangement as defined in claim 1 wherein the transmitted and received signal comprises two sequential ultrasonic signals at different frequencies with the first ultrasonic signal being at said predetermined frequency and having a time duration which determines the type of instruction and the second ultrasonic signal being at a different predetermined frequency and effecting the performance of the received instruction represented by said first signal.
Claim 6
Dependent Claim
68 words
An ultrasonic remote control apparatus as defined in claim 4 further comprising: means for receiving said ultrasonic signals and for converting same to said pulses; and means responsive to a pulse indicating receipt of said second ultrasonic signal for interrupting the feeding of said pulses to said counter and for causing the contents of said memory to be readout to a control circuit for carrying out the instruction.
Claim 7
Dependent Claim
66 words
A circuit arrangement as defined in claim 1 wherein said logic means includes a first logic gate connected between the output of said means for feeding and the counting input of said counter and a second logic gate whose inputs are connected to selected outputs of said counter and whose output is connected to an input of said first logic gate and to said memory means.
Claim 8
Dependent Claim
38 words
A circuit arrangement as defined in claim 6 wherein said first logic gate is responsive to an output signal from said second logic gate to interrupt the feeding of said pulses to the counting input of said counter.
Claim 9
Dependent Claim
17 words
A circuit arrangement as defined in claim 7 wherein the first logic gate is a NAND gate.
Claim 10
Dependent Claim
63 words
A circuit arrangement as defined in claim 7 wherein said second logic gate is a NAND gate which has two inputs connected to selected outputs of the counter which are associated with said counter state corresponding to said maximum predetermined time duration and whose output potential changes from logic "1" to "0" whenever said selected outputs of said counter are at logic "1".
Claim 11
Dependent Claim
40 words
A circuit arrangement as defined in claim 9 wherein said memory is a forward-backward counter and wherein the memory contents are erased whenever the potential at the output of said second logic gate changes from logic "1" to logic "0".
References Cited (Backward Citations)
US3651469A
Cited
US3798601A
Cited
US3855575A
Cited
US3900880A
Cited
US3953832A
Cited
US3914698A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-11 | 1980-07-12 | 1981-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-11 | 1984-07-12 | 1985-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-11 | 1988-07-12 | 1989-01-11 | $7700.00 | Window Closed / Lapsed |