US4001699A
Expired / Lapsed
US
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Bar graph digital interface circuit
Assignee: Unisys Corp
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Filing: 1975-09-15
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Granted: 1977-01-04
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Expires: 1995-09-15
Abstract
Abstract A circuit for controlling the height of a bar graph display in response to a digital input signal. A first count, representing the particular cathode segment of the bar graph under energization, is developed by a counter which monitors the clock signal driving the bar graph display. A second count is developed by a counter stepped by a clock when the digital input signal is in a selected logic state. At the end of a selected interval, the counters contents are transferred to a register for supply to a digital comparator, which compares the first and second counts and produces a control signal upon their equality.
Inventors
- 👤 William Michael Denny
- 👤 Russell Louis Hagen
- 👤 Steve Ka-Lai Leung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 11:38
CPC Classifications
G; G01; G01R; G01R13/00; G01R13/40; G01R13/404; G01R13/405; G06; G06F; G06F11/00; G06F11/30; G06F11/34; G06F11/3466; G06F11/348; H; H03; H03M; H03M1/00; H03M1/12; H03M1/22; H03M1/24; H03M1/28; H03M1/287; G06F11/32; G06F11/323
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
346 words
Display interface circuitry responsive to a selected logic state of a digital input signal for producing a control signal for controlling a bar graph display including a plurality of sequentially activated cathode segments cooperating with a single anode element comprising: first count producing means for producing a first count indicating the particular cathode segment under activation at any time; second count producing means for producing a second count proportional to the duration of said digital signal in said selected logic state; and means for comparing said first count to said second count and producing said control signal upon their equivalence; said second count producing means including: first clock means for producing a first clock signal having a frequency equal to the product of the total number of said plurality of cathode segments and 2 N where N equals an integer 0, 1, 2, 3 . . . ; logic means supplied with said first clock signal for producing sampling clock pulses when said digital signal is in said selected logic state; and first counter means for counting said sampling clock pulses; and said first count producing means comprising: second clock means for producing second clock pulses of a frequency equal to the produce of the total number of said plurality of cathode segments and the number of times per second said plurality of cathode segments is to be sequentially energized; second counter means for counting a number of said second clock pulses equal to the total number of said plurality of cathode segments and thereafter resetting; said second count producing means further including: third counter means driven by said first clock signal for counting to the product of 2 N and the total number of said plurality of cathode elements and thereupon producing a reset signal; register means responsive to said reset signal for storing at least the high order count bits of said second counter means necessary to represent the total number of said plurality of cathode elements; and delay means activated by said reset signal for resetting said second counter means after said storing.
Claim 2
Dependent Claim
346 words
Display interface circuitry responsive to a selected logic state of a digital input signal for producing a control signal for controlling a bar graph display including a plurality of sequentially activated cathode segments cooperating with a single anode element comprising: first count producing means for producing a first count indicating the particular cathode segment under activation at any time; second count producing means for producing a second count proportional to the duration of said digital signal in said selected logic state; and means for comparing said first count to said second count and producing said control signal upon their equivalence; said second count producing means including: first clock means for producing a first clock signal having a frequency equal to the product of the total number of said plurality of cathode segments and 2 N where N equals an integer 0, 1, 2, 3 . . . ; logic means supplied with said first clock signal for producing sampling clock pulses when said digital signal is in said selected logic state; and first counter means for counting said sampling clock pulses; and said first count producing means comprising: second clock means for producing second clock pulses of a frequency equal to the produce of the total number of said plurality of cathode segments and the number of times per second said plurality of cathode segments is to be sequentially energized; second counter means for counting a number of said second clock pulses equal to the total number of said plurality of cathode segments and thereafter resetting; said second count producing means further including: third counter means driven by said first clock signal for counting to the product of 2 N and the total number of said plurality of cathode elements and thereupon producing a reset signal; register means responsive to said reset signal for storing at least the high order count bits of said second counter means necessary to represent the total number of said plurality of cathode elements; and delay means activated by said reset signal for resetting said second counter means after said storing.
Claim 3
Dependent Claim
40 words
The display interface circuitry of claim 1 wherein said comparing means comprises: digital comparator means for comparing the count of said first counter means with the bits in said register means and for producing said control signal upon their equivalence.
Claim 4
Dependent Claim
194 words
The combination of a bar graph display and display interface circuitry responsive to a selected logic state of a digital input signal for producing a control signal for controlling the height of said bar graph display in accordance with the length of time that said digital input signal is in said selected logic state; said bar graph display including a plurality of sequentially activated cathode segments cooperating with a single anode element; and said display interface circuitry comprising: first count producing means for producing a first count indicating the particular cathode segment of said bar graph display which is under activation at any time; second count producing means for producing a second count proportional to the duration of said digital signal in said selected logic state, said second count producing means including means for updating said second count at a predetermined cyclic rate; and comparing means for comparing said first count to said second count and producing said control signal upon their equivalence; and means for applying said control signal to said bar graph display along with said first count from said first count producing means for controlling the height of said bar graph.
Claim 5
Dependent Claim
194 words
The combination of a bar graph display and display interface circuitry responsive to a selected logic state of a digital input signal for producing a control signal for controlling the height of said bar graph display in accordance with the length of time that said digital input signal is in said selected logic state; said bar graph display including a plurality of sequentially activated cathode segments cooperating with a single anode element; and said display interface circuitry comprising: first count producing means for producing a first count indicating the particular cathode segment of said bar graph display which is under activation at any time; second count producing means for producing a second count proportional to the duration of said digital signal in said selected logic state, said second count producing means including means for updating said second count at a predetermined cyclic rate; and comparing means for comparing said first count to said second count and producing said control signal upon their equivalence; and means for applying said control signal to said bar graph display along with said first count from said first count producing means for controlling the height of said bar graph.
Claim 6
Dependent Claim
77 words
The display interface circuitry of claim 3 wherein said first count producing means comprises: clock means for producing clock pulses of a frequency equal to the product of the total number of said plurality of cathode segments and the number of times per second said plurality of cathode segments are to be sequentially energized; and counter means for counting a number of said clock pulses equal to the total number of said cathode segments and thereafter resetting.
Claim 7
Dependent Claim
90 words
The display interface circuitry of claim 3 wherein said second count producing means also includes: first clock means for producing a first clock signal having a frequency equal to the product of the total number of said plurality of cathode segments and 2 N where N equals an integer 0, 1, 2, 3 . . . ; logic means supplied with said first clock signal for producing sampling clock pulses when said digital signal is in said selected logic state; and first counter means for counting said sampling clock pulses.
Claim 8
Dependent Claim
82 words
The display interface circuitry of claim 5 wherein said first count producing means comprises: second clock means for producing second clock pulses of a frequency equal to the product of the total number of said plurality of cathode segments and the number of times per second said plurality of cathode segments is to be sequentially energized; second counter means for counting a number of said second clock pulses equal to the total number of said plurality of cathode segments and thereafter resetting.
Claim 9
Dependent Claim
105 words
The display interface circuitry of claim 6 wherein said means for updating includes third counter means driven by said first clock signal for counting to the product of 2 N and the total number of said plurality of cathode elements and thereupon producing a reset signal, and wherein said second count producing means further includes: register means responsive to said reset signal for storing at least the high order count bits of said second counter means necessary to represent the total number of said plurality of cathode elements; and delay means activated by said reset signal for resetting said second counter means after said storing.
Claim 10
Dependent Claim
40 words
The display interface circuitry of claim 7 wherein said comparing means comprises: digital comparator means for comparing the count of said first counter means with the bits in said register means and for producing said control signal upon their equivalence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-04 | 1980-07-05 | 1981-01-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-04 | 1984-07-05 | 1985-01-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-04 | 1988-07-05 | 1989-01-04 | $7700.00 | Window Closed / Lapsed |