Solid state crosspoint circuit arrangement for use in a telephone exchange

Claim 2

A solid state crosspoint comprising first and second transistor means each arranged to operate in its linear region, each of said transistors having an emitter electrode, a collector electrode and a base electrode, the emitter electrodes affording inputs to said crosspoint and the collector electrodes affording outputs of said crosspoint and bias means connected to the base electrodes of the first and second transistors for causing them to be biased so that they operate in current driven, common base configuration.

Claim 3

A crosspoint according to claim 1, in which the bias means is a memory device having ON and OFF states and in which memory trigger means is provided for setting the state of said memory device.

Claim 4

A crosspoint according to claim 2, in which the memory device takes the form of a silicon controlled rectifier memory.

Claim 5

A crosspoint according to claim 3, in which the silicon controlled rectifier memory is constituted by a PNP transistor and an NPN transistor, the collector electrode of the PNP transistor being connected to the base electrode of the NPN transistor, and the collector electrode of the NPN transistor being connected to the base electrode of the PNP transistor and via resistor means to the emitter electrode of the PNP transistor, the collector electrode of the NPN transistor constituting the trigger electrode of said memory.

Claim 6

A crosspoint according to claim 4, in which the first and second transistor means are each constituted by a NPN transistor, the base electrodes thereof being connected together and connected to the emitter electrode of the NPN transistor of the silicon controlled rectifier memory, the emitter electrode of the PNP transistor of said memory being connected to a supply voltage and the collector electrode of the NPN transistor of said memory being connected to the memory trigger means.

Claim 7

A crosspoint matrix arrangement comprising a matrix array of solid state crosspoints according to claim 1, said crosspoints being electrically interconnected in rows and in columns, the emitter electrodes of the first transistor means of the said crosspoints of each row being interconnected, the collector electrodes of the second transistor means of the said crosspoints of each row being interconnected, the emitter electrodes of the second transistor means of the said crosspoints of each column being interconnected and the collector electrodes of the first transistor means of the said crosspoints of each column being interconnected.

Claim 8

A crosspoint matrix arrangement according to claim 6, comprising voltage level translator means associated with each row and with each column of said matrix arrangement, the voltage level translator means being connected in series with the collector electrodes of the first or second transistor means.

Claim 9

A crosspoint matrix arrangement according to claim 6, in which mark detector means is provided associated with the emitter electrodes of the first transistor means of the crosspoints of each row of said matrix arrangement and means is included for providing a current path for the bias means of said row and for causing mark generator means associated with the collector electrodes of the first transistor means of the said crosspoints of each column of said matrix arrangement to be activated.

Claim 10

A crosspoint matrix arrangement according to claim 8, in which mark generator inhibitor means is provided associated with each of the mark generator means for inhibiting the activation thereof if any one of the crosspoints of the associated column of said matrix arrangement is biased ON.

Claim 11

A crosspoint matrix arrangement according to claim 7, in which current detector means is provided associated with each of the voltage level translator means of each column of said matrix arrangement, for connecting a supply voltage to the silicon controlled rectifier memories of the crosspoints of the associated column.

Claim 12

A plurality of crosspoint matrix arrangements according to claim 6 connected in the form of a switchblock.

Claim 13

A switchblock according to claim 11, comprising a plurality of stages, each stage of the switchblock including a plurality of crosspoint matrix arrangements which are interconnected in `mushroom` configuration.