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US3987292A Expired / Lapsed US ⏱️ 0.0 years remaining

Discrete Fourier transform via cross correlation charge transfer device

Assignee: United States Department of the Navy
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Filing: 1975-06-02
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Granted: 1976-10-19
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Expires: 1995-06-02
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Abstract

Abstract A circuit for generating a discrete Fourier transform in real time employs a digital and analog shift register, each cell of which is tapped to feed an analog switch. The outputs of the individual analog switches are fed to a summing bus where the switched analog signals combine to form the desired Fourier transform.

Inventors

  • 👤 Robert W. Means

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 15:07
CPC Classifications
G; G06; G06J; G06J1/00; G06J1/005

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 178 words
A signal processor to produce a Fourier transform of an analog signal having a plurality of data points comprising: digital shift register means having a plurality of cells for recirculating a digital clocking signal; a charge coupled device configured as an analog shift register means having a plurality of cells for receipt and circulation of an analog signal at a predetermined rate different from that of said digital shift register; a plurality of analog switch circuits each connected to a cell of said digital shift register by means of a direct, unweighted tap and connected to a corresponding cell of said analog shift register by means of a weighted tap which is weighted according to the expression; e.sup.i.sup.πk.spsp.2/2N where; k = integers between 0 and (N-1), and N = one-half the number of cells in said analog shift registers plus one; and summing means connected to each of said plurality of analog switches for receipt of the switched outputs therefrom, whereby a composite Fourier transform of the analog signal received by said analog shift register means is obtained.
Claim 2
Dependent Claim 178 words
A signal processor to produce a Fourier transform of an analog signal having a plurality of data points comprising: digital shift register means having a plurality of cells for recirculating a digital clocking signal; a charge coupled device configured as an analog shift register means having a plurality of cells for receipt and circulation of an analog signal at a predetermined rate different from that of said digital shift register; a plurality of analog switch circuits each connected to a cell of said digital shift register by means of a direct, unweighted tap and connected to a corresponding cell of said analog shift register by means of a weighted tap which is weighted according to the expression; e.sup.i.sup.πk.spsp.2/2N where; k = integers between 0 and (N-1), and N = one-half the number of cells in said analog shift registers plus one; and summing means connected to each of said plurality of analog switches for receipt of the switched outputs therefrom, whereby a composite Fourier transform of the analog signal received by said analog shift register means is obtained.
Claim 3
Dependent Claim 28 words
A signal generator according to claim 1 in which the signal transfer rate of the said analog shift register is one half that of said digital shift register.
Claim 4
Dependent Claim 53 words
A signal processor circuit according to claim 1 in which said digital shift register means, said analog shift register means and said plurality of analog switch circuits have a number of cells and individual circuits, respectively, equal to one less than twice the number of the data points of the desired Fourier transform.
Claim 5
Dependent Claim 29 words
A signal processor according to claim 3 in which the signal transfer rate of the aforesaid analog shift register is one half that of the aforesaid digital shift register.

References Cited (Backward Citations)

US3449553A Cited
US3474260A Cited
US3598979A Cited
US3704826A Cited
US3670151A Cited
US3643106A Cited
US3831013A Cited
US3903406A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1979-10-19 1980-04-19 1980-10-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1983-10-19 1984-04-19 1984-10-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1987-10-19 1988-04-19 1988-10-19 $7700.00 Window Closed / Lapsed

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