US3984833A
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Apparatus for encoding extended run-length codes
Assignee: International Business Machines Corp
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Filing: 1975-07-17
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Granted: 1976-10-05
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Expires: 1995-07-17
Abstract
Abstract Apparatus for encoding ordinary run-length codes and run-length codes that have been extended to include two classes of code words, regular code words for runs and special code words for selected special situations. The encoder comprises table storage, select/combine circuitry, and shift-out circuitry. The table storage holds four small tables whose values can be adjusted to correspond to any ordinary or extended run-length code to be implemented. The select/combine circuitry accepts as input a binary value that uniquely identifies the desired code word, and combines this binary value with selected table values to calculate the desired code word. The code word bits are then outputted sequentially by the shift-out circuitry.
Inventors
- 👤 David Curtis Van Voorhis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:27
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/90; H04N19/93; H03; H03M; H03M7/00; H03M7/30; H03M7/40; H03M7/4025; H03M7/42; H03M7/46; H04N1/00; H04N1/41; H04N1/411; H04N1/413; H04N1/419
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
167 words
An apparatus for encoding binary event designations for various ordinary and extended run-length codes, the codes comprising up to N regular code words c r (1), c r (2), . . . and up to M special code words c s (1), c s (2), . . . whose code word lengths are ordered and bounded according to the two relations l ≦ l.sub.r (1) ≦ l.sub.r (2) ≦ . . . ≦ l.sub.max, l ≦ l.sub.s (1) ≦ l.sub.s (2) ≦ . . . ≦ l.sub.max, where l max is a chosen integer greater than or equal to log 2 (N+M), the apparatus comprising: table storage for tables whose values can be adjusted to correspond to any ordinary or extended run-length code to be implemented; select/combine circuitry for accepting a binary event designation value, for selecting corresponding table values, and for combining these table values with the event designation value to calculate a code word; and shift-out circuitry for serially outputting the successive code word bits.
Claim 2
Independent Claim
167 words
An apparatus for encoding binary event designations for various ordinary and extended run-length codes, the codes comprising up to N regular code words c r (1), c r (2), . . . and up to M special code words c s (1), c s (2), . . . whose code word lengths are ordered and bounded according to the two relations l ≦ l.sub.r (1) ≦ l.sub.r (2) ≦ . . . ≦ l.sub.max, l ≦ l.sub.s (1) ≦ l.sub.s (2) ≦ . . . ≦ l.sub.max, where l max is a chosen integer greater than or equal to log 2 (N+M), the apparatus comprising: table storage for tables whose values can be adjusted to correspond to any ordinary or extended run-length code to be implemented; select/combine circuitry for accepting a binary event designation value, for selecting corresponding table values, and for combining these table values with the event designation value to calculate a code word; and shift-out circuitry for serially outputting the successive code word bits.
Claim 3
Dependent Claim
71 words
An apparatus according to claim 1, wherein the table storage holds a BR table, and BS table, a TR table, and a TS table whose elements are related to the code word lengths for the code to be implemented by the formulas: b r (k) = number of regular code words with length k or less; b s (k) = number of special code words with length k or less; ##EQU3##
Claim 4
Dependent Claim
216 words
An apparatus according to claim 2, wherein the select/combine circuitry comprises: means for accepting a binary event designation value comprising a one-bit integer s and a multibit integer i, with the value s=0 indicating that the ith regular code word c r (i) is to be generated, and with the value s=1 indicating that the ith special code word c s (i) is to be generated; means for comparing i with successive elements of the BR table until a table value b r (k) is found to satisfy b r (k)≧i, if s=0, or for comparing i with successive elements of the BS table until a table value b s (k) is found to satisfy b s (k)≧ i, if s=1; means for selecting a corresponding element t r (k) from the TR table if s=0, or for selecting a corresponding element t s (k) from the TS table, if s=1; and means for combining i with the selected table elements to calculate the l max -bit binary integer ##EQU4## whose leftmost k bits comprise the desired regular code word c r (i) = t r (k) - b r (k) + i-l, if s=0, or the desired special code word c s (i) = t s (k) - b s (k) + i-l, if s=1.
Claim 5
Dependent Claim
28 words
An apparatus according to claim 3 wherein the shift-out circuitry serially outputs the k leftmost bits of the l max -bit integer C calculated by the shift-out circuitry.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-10-05 | 1980-04-05 | 1980-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-10-05 | 1984-04-05 | 1984-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-10-05 | 1988-04-05 | 1988-10-05 | $7700.00 | Window Closed / Lapsed |