Digital dc motor velocity control system

Claim 2

In a control system for a motor having an armature with drive circuit means for energizing said armature and having emitter means driven by said armature for producing feedback pulses, first free running counter means reset by said feedback pulses for recording the feedback period; decode latch means responsive to said first counter means for determining whether the feedback period is long or short; trigger means for storing the status of said decode latch; an up/down counter responsive to said feedback pulses and gated by said trigger means for adjusting the motor drive pulse width; second free running counter means reset by said feedback pulses to terminate the drive to the motor; and comparing means responsive to said up/down counter and said second free running counter means for controlling said motor drive circuit means to maintain a precise motor velocity.

Claim 3

In a control system for a motor having an armature with drive circuit means for energizing said armature and having emitter means driven by said armature for producing feedback pulses; oscillator means; first free running counter means driven by said oscillator means and reset by said feedback pulses for recording the feedback period; decode latch means set to a value to represent the desired time period between said feedback pulses and responsive to said first free running counter means for determining whether the feedback period is long or short; trigger means reset by said feedback pulses and set by said decode latch means for storing the status of the decode latch; an up-down counter responsive to said feedback pulses and gated into an up count mode or a down count mode depending on the status of said trigger means; second free running counter means driven by said oscillator means and reset by said feedback pulses to terminate the drive to the motor; and comparing means responsive to the output of said up-down counter and the output of said second free running counter means for providing drive pulses to said motor drive circuit means to maintain a precise motor velocity.

Claim 4

In a control system for a motor having an armature with drive circuit means for energizing said armature and having emitter means driven by said armature for producing feedback pulses; oscillator means; first free running counter means driven by said oscillator means and reset by said feedback pulses for recording the feedback period; decode latch means set to a value to represent the desired time period between said feedback pulses and responsive to said first free running counter means for determining whether the feedback period is long or short; trigger means reset by said feedback pulses and set by said decode latch means for storing the status of the decode latch; an up-down counter responsive to said feedback pulses and gated into an up count mode or a down count mode depending on the status of said trigger means; second free running counter means driven by said oscillator means and reset by said feedback pulses to terminate the drive to the motor; and comparing means responsive to the output of said up-down counter and the output of said second free running counter means for providing drive pulses to said motor drive circuit means to maintain a precise motor velocity.

Claim 5

The control system as defined in claim 2 and including delay means for the reset of said trigger means to provide sufficient response time for said up-down counter.

Claim 6

In a control system for a motor having an armature with drive circuit means for energizing said armature and having emitter means driven by said armature for producing feedback pulses; oscillator means; first free running counter means driven by said oscillator means and reset by said feedback pulses for recording the feedback period; decode latch means set to a value to represent the desired time period between said feedback pulses and connected to the output of said first free running counter means; trigger means reset by said feedback pulses and set by the output of said decode latch means when the value in said first free running counter means equals or exceeds the value in said decode latch means; an up-down counter responsive to said feedback pulses and gated in a count down mode when said trigger means is set; second free running counter means driven by said oscillator means and reset by said feedback pulses to terminate the drive to the motor; and comparing means responsive to the output of said up-down counter and the output of said second free running counter means and effective to provide a drive pulse to the motor drive circuit means only when the output value of said second free running counter means equals or exceeds the output value of the up-down counter.

Claim 7

In a control system for a motor having an armature with drive circuit means for energizing said armature and having emitter means driven by said armature for producing feedback pulses; oscillator means; first free running counter means driven by said oscillator means and reset by said feedback pulses for recording the feedback period; decode latch means set to a value to represent the desired time period between said feedback pulses and connected to the output of said first free running counter means; trigger means reset by said feedback pulses and set by the output of said decode latch means when the value in said first free running counter means equals or exceeds the value in said decode latch means; an up-down counter responsive to said feedback pulses and gated in a count down mode when said trigger means is set; second free running counter means driven by said oscillator means and reset by said feedback pulses to terminate the drive to the motor; and comparing means responsive to the output of said up-down counter and the output of said second free running counter means and effective to provide a drive pulse to the motor drive circuit means only when the output value of said second free running counter means equals or exceeds the output value of the up-down counter.

Claim 8

The control system as defined in claim 3 wherein said trigger means remains in a reset stage when the value in said first free running counter means is less than the value in said decode latch means, and said up-down counter is gated in an up count mode when said trigger means is in the reset stage.

Claim 9

In a control system for a motor having an armature with drive circuit means for energizing said armature and having emitter means driven by said armature for producing feedback pulses; oscillator means; first free running counter means driven by said oscillator means and reset by said feedback pulses for recording the feedback period; decode latch means preset to a value to represent the desired time period between said feedback pulses and connected to the output of said first free running counter means; said decode latch means producing an output pulse when the value in said first free running counter means equals or exceeds said preset value indicating that the feedback period is in excess of the period desired and the motor speed is too slow and producing no output pulse when the value in said first free running counter means is less than said preset value indicating that the feedback period is less than the period desired and the motor speed is too fast; trigger means reset by said feedback pulses and set by an output pulse from said decode latch means; an up-down counter responsive to said feedback pulses and gated in a count down mode when said trigger means is set and in a count up mode when said trigger means is in a reset stage, whereby the contents of said up-down counter is varied to reflect motor speed variance; second free running counter means driven by said oscillator means and reset by said feedback pulses to terminate the drive to the motor; and comparing means responsive to the output of said up-down counter and the output of said second free running counter means and effective to provide a drive pulse to the motor drive circuit means only when the output value of said second free running counter means equals or exceeds the output value of the up-down counter.

Claim 10

In a control system for a motor having an armature with drive circuit means for energizing said armature and having emitter means driven by said armature for producing feedback pulses; oscillator means; first free running counter means driven by said oscillator means and reset by said feedback pulses for recording the feedback period; decode latch means preset to a value to represent the desired time period between said feedback pulses and connected to the output of said first free running counter means; said decode latch means producing an output pulse when the value in said first free running counter means equals or exceeds said preset value indicating that the feedback period is in excess of the period desired and the motor speed is too slow and producing no output pulse when the value in said first free running counter means is less than said preset value indicating that the feedback period is less than the period desired and the motor speed is too fast; trigger means reset by said feedback pulses and set by an output pulse from said decode latch means; an up-down counter responsive to said feedback pulses and gated in a count down mode when said trigger means is set and in a count up mode when said trigger means is in a reset stage, whereby the contents of said up-down counter is varied to reflect motor speed variance; second free running counter means driven by said oscillator means and reset by said feedback pulses to terminate the drive to the motor; and comparing means responsive to the output of said up-down counter and the output of said second free running counter means and effective to provide a drive pulse to the motor drive circuit means only when the output value of said second free running counter means equals or exceeds the output value of the up-down counter.

Claim 11

A control system as defined in claim 6 and including inverter means connecting said oscillator means with said decode latch means whereby said decode latch means is prevented from evaluating the outputs from said first free running counter means during input pulse times to said first free running counter means.

Claim 12

A control system as defined in claim 6 and including AND gate and inverter circuit means connected between the output and input of said second free running counter means to prevent an overflow when it reaches a maximum count.

Claim 13

A control system as defined in claim 6 and including AND gate and inverter circuit means connected between the output of said up-down counter and the output of said trigger means to prevent the up-down counter from being gated in the count up mode upon the presence of all bits on its output and also to prevent the counter from being gated in the count down mode for a no bit condition on its output.