Digital acceleration detecting system

Claim 2

A digital acceleration detecting system comprising: detecting means for generating pulse signals having a frequency corresponding to the speed of a rotating body to be detected; a first counter for counting said pulse signals from said detecting means during a predetermined period of time; a second counter for counting said pulse signals during said predetermined period of time which begins at a time different by a unit time from the time of the beginning of the counting by said first counter; an oscillator for generating clock pulses of a constant frequency; and control means for blocking the pulse signals from the detecting means after the elapse of both of the predetermined periods of said counters, for applying the clock pulses from said oscillator to said counters simultaneously for continuing the counts accumulated by said counters during said predetermined periods of time, and for generating an output pulse with a duration from the time when the count of said first counter reaches a predetermined value until the time when the count of said second counter reaches a predetermined value.

Claim 3

A digital acceleration detecting system according to claim 1, wherein said detecting means includes speed sensor for generating pulse signals with a frequency corresponding to the rotational speed of the wheel.

Claim 4

A digital acceleration detecting system according to claim 1, wherein said first and second counters each count in the same polarity.

Claim 5

A digital acceleration detecting system comprising: detecting means for generating pulse signals having a frequency corresponding to the speed of a rotating body to be detected; an oscillator for generating clock pulses with a constant frequency; a first gate means connected to said detecting means and said oscillator, for passing the pulse signals from said detecting means for a predetermined period, and for blocking said pulse signals thereafter and passing the clock pulses from said oscillator after the elapse of a given time of the blocking; a second gate means connected in parallel with said first gate means, for passing the pulse signals from said detecting means for a predetermined period from the time delayed by a given period from the beginning of the gating of said first gate means, and for blocking said pulse signals immediately thereafter and passing the clock pulses from said oscillator simultaneously with said first gate means; a first counter connected to said first gate means, for counting said pulse signals and said clock pulses passed by the gating of said first gate means; a second counter connected to said second gate means, for counting said pulse signals and said clock pulses passed by the gating of said second gate means; and a third gate means for generating an output pulse having duration from the time when the count of said first counter reaches a predetermined value until the time when the count of said second counter reaches a predetermined value.

Claim 6

A digital acceleration detecting system comprising: detecting means for generating pulse signals having a frequency corresponding to the speed of a rotating body to be detected; an oscillator for generating clock pulses with a constant frequency; a first gate means connected to said detecting means and said oscillator, for passing the pulse signals from said detecting means for a predetermined period, and for blocking said pulse signals thereafter and passing the clock pulses from said oscillator after the elapse of a given time of the blocking; a second gate means connected in parallel with said first gate means, for passing the pulse signals from said detecting means for a predetermined period from the time delayed by a given period from the beginning of the gating of said first gate means, and for blocking said pulse signals immediately thereafter and passing the clock pulses from said oscillator simultaneously with said first gate means; a first counter connected to said first gate means, for counting said pulse signals and said clock pulses passed by the gating of said first gate means; a second counter connected to said second gate means, for counting said pulse signals and said clock pulses passed by the gating of said second gate means; and a third gate means for generating an output pulse having duration from the time when the count of said first counter reaches a predetermined value until the time when the count of said second counter reaches a predetermined value.

Claim 7

A digital acceleration detecting system comprising: detecting means for generating pulse signals having a frequency corresponding to the speed of a rotating body to be detected; a first counter for counting said pulse signals from said detecting means during a predetermined period of time; a second counter for counting said pulse signals during said predetermined period of time which begins at a time different by a unit time from the time of the beginning of the counting by said first counter; an oscillator for generating clock pulses with a constant frequency; and control means for blocking the pulse signals from said detecting means after the elapse of both of the predetermined periods of said counters, and for applying the clock pulses from said oscillator to said counters for a further period whereby the control means generates an output pulse having a duration corresponding to the difference between the counts of said counters just before the application of said clock pulses.

Claim 8

A digital acceleration detecting system comprising: detecting means for generating pulse signals having a frequency corresponding to the speed of a rotating body to be detected; a first counter for counting said pulse signals from said detecting means during a predetermined period of time; a second counter for counting said pulse signals during said predetermined period of time which begins at a time different by a unit time from the time of the beginning of the counting by said first counter; an oscillator for generating clock pulses with a constant frequency; and control means for blocking the pulse signals from said detecting means after the elapse of both of the predetermined periods of said counters, and for applying the clock pulses from said oscillator to said counters for a further period whereby the control means generates an output pulse having a duration corresponding to the difference between the counts of said counters just before the application of said clock pulses.