Character generator system selectively providing different dot-matrix size symbols

Claim 2

In a character generator system for digitally generating symbols for display on a display device exhibiting a television raster scan, said system comprising: a character generator memory having a predetermined fixed overall bit storage capacity for storing each respective one of a plurality of different symbols in two-dimensional dot-matrix form at a separate address location thereof, the dot matrix at all address locations having the same size first-dimension and the same size second-dimension; multibit shift register means having a number of stages at least equal to the size of said first dimension; timing and control logic synchronized with said television raster scan; first means, controlled by said timing and control logic and including a refresh memory page of stored multibit symbol codes defining the message to be displayed, for addressing said character generator memory during any scan line at the beginning of every successive symbol display interval with a multibit symbol dot pattern address word, said symbol dot pattern address word including a symbol code portion defining the character-generatormemory location of the symbol to be displayed in that symbol display interval and a scan-line code portion defining the ordinal position corresponding to the scan line then in progress in the dot matrix second dimension, whereby said character generator memory produces a parallel multibit dot pattern word output at least equal in size to the first dimension size of said dot matrix, at least a portion of said dot pattern word defining the portion of said symbol to be displayed in that symbol display interval which occurs during the scan-line then in progress; and second means controlled by said timing and control logic for loading stages of said shift register means with at least said portion of said parallel multibit dot pattern word output and then shifting said loaded word output from said shift register means with dot clock pulses during that symbol display interval; the improvement wherein: a. said character generator memory is a read/write memory which may be programmed to store symbols In any selected single one of a given number of different predetermined dot-matrix sizes, with the number of different symbols and corresponding address locations therefor which can be accommodated being relatively larger for relatively small dot-matrix sizes than for relatively large dot-matrix sizes, and said system includes a dot-matrix register for registering therein the dot-matrix size that has been selected; b. wherein said first means includes memory address organization logic coupled to said register and responsive to the registration therein for selecting the number of bits of the multibit symbol code from said refresh memory page assigned to the symbol code portion of said symbol dot pattern address word and for selecting the number of bits in said scan-line code portion of said dot pattern address word in accordance with the size of said second dimension of said dot matrix; and c. said second means includes dot pattern selection, load and clock logic coupled to said display refresh memory page and said register and responsive to the registration therein and the binary value of at least one predetermined bit of said multibit symbol code for selectively loading the stages of said shift register means with said bits of said parallel multibit dot pattern word output and shifting said shift register means to provide a serial sequence of the total number of dots in the first dimension of said selected size of dot matrix during each successive symbol display interval.

Claim 3

The system defined in claim 1, wherein the total number of bits in said multibit symbol dot pattern address word is the same for all of said given number of different predetermined dot-matrix sizes, whereby the sum of the selected number of bits assigned to the symbol code portion and the selected number of bits in the scan-line portion of said symbol dot pattern address word is a constant which is independent of the registration in said dot-matrix register.

Claim 4

The system defined in claim 2, a. wherein said character generator memory comprises four memory blocks each having a storage capacity of 1024 16-bit words and said symbol dot pattern address word is a ten-bit word which is simultaneously applied as an input to all of said four memory blocks, b. wherein said different predetermined dot-matrix sizes include a 32 X 32 size, a 21 X 32 size, a 16 X 32 size and a 16 X 16 size, c. wherein said memory organization logic assigns five of the ten bit symbol dot pattern address words to said symbol code portion thereof and the remaining five of the ten bits of said symbol dot pattern address word to said scan-line code portion thereof in response to any of said 32 X 32, 21 X 32 or 16 X 32 dot matrix sizes being selected by the registration in said dot-matrix register and assigns six of the ten bits of said symbol dot pattern address word to said symbol code portion thereof and the remaining four bits of the ten bits of said symbol dot pattern address word to said scan-line code portion thereof in response to said 16 X 16 dot matrix size being selected by the registration in said dot matrix register, d. wherein said shift register means is a shift register having at least thirty-two stages; e. wherein said dot pattern selection, load and clock logic include memory output dot selection logic, which in response to: (1) selection of said 32 X 32 dot matrix loads thirty-two consecutive stages of said shift register with the respective 16-bit dot pattern word outputs from each of a given pair of said four memory blocks only when a first predetermined bit of said multibit symbol code manifests a given binary value, or with the 16-bit dot pattern word output from each of the remaining pair of said four memory blocks only when said first preselected bit manifests the complement of said given binary value, (2) selection of said 21 X 32 dot matrix loads twenty-one consecutive stages of said shift register wIth both the 16 bit dot pattern word output from a first of said four memory blocks and a first given five-bit portion of the 16 bit dot pattern word output from a second of said four memory blocks only when said first and second preselected bits of said multibit symbol code taken together manifest a first given binary value, or with both a first given five-bit portion of the 16 bit dot pattern word output from a third of said four memory blocks and the 16 bit dot pattern word from a fourth of said four memory blocks only when said first and second preselected bits taken together manifest a second given binary value different from said first given binary value, or with both a second given eleven-bit portion of the sixteen bit dot pattern word output from the second of said four memory blocks and a second given ten-bit portion of the 16 bit dot pattern word output from the third of said four memory blocks only when said first and second preselected bits taken together manifest a third given binary value different from both said first and second given binary values, and (3) selection of either said 16 X 32 or said 16 X 16 dot matrix loads sixteen consecutive stages of said shift register with the 16 bit dot pattern word output from a first of said four memory blocks only when first and second preselected bits of said multibit symbol code taken together manifest a first given binary value, or with the 16 bit dot pattern word output when said first and second preselected bits taken together manifest a second given binary value different from said first given binary value, or with the 16 bit dot pattern word output from a third of said four memory blocks only when said first and second preselected bits taken together manifest a third given binary value different from both said first and second given binary values, or with the 16 bit dot pattern word output from a fourth of said four memory blocks only when said first and second preselected bits taken together manifest a fourth given binary value different from each of said first, second and third given binary values, and f. wherein said dot pattern selection, load and clock logic also include dot load pulse logic for effecting a loading of said shift register at the beginning of each successive sequence of thirty-two consecutive dot clock shift pulses only when said 32 X 32, 21 X 32 or 16 X 32 dot matrix size is selected by the registration in said dot matrix register, and effecting a loading of said register at the beginning of each sequence of 16 consecutive dot clock shift pulses only when said 16 X 16 dot matrix size is selected by the registration in said dot matrix register.

Claim 5

The system defined in claim 1, a. wherein said shift register means includes first and second shift registers each having at least n stages, and an OR gate for combining the outputs of said first and second shift registers, b. wherein said dot matrix sizes includes a first dot matrix having a first dimension equal to n and a second dot matrix having a first dimension equal to 2n, c. wherein said dot pattern selection, load and clock logic includes coupling means responsive to a load pulse applied to said first shift register for loading said n stages of said first shift register with a first group of n bits of said dot pattern word output, said coupling means being responsive to a load pulse being applied to said second shift register for loading said n stages of said second shift register with a second group of n bits of said dot pattern word output, and d. wherein said dot pattern selection, load and clock logic further includes dot load/clock pulse generation logic responsive to (1) selection of said first dot matrix for applying load pulses and a first series of dot clock shift pulses having a given dot period solely to said first shift register only when a preselected bit of said multibit symbol clock manifests a given binary value or for applying said load pulses and said first series of dot clock shift pulses solely to said second shift register only when said preselected bit manifests the complement of said given binary value, a load pulse occurring at the beginning of each successive sequence of n dot clock shift pulses of said first series, each load pulse having a duration substantially equal to said given dot period, and (2) selection of said second dot matrix for applying said load pulses and said first series of dot clock shift pulses to said first shift register and simultaneously therewith applying said load pulses and a second series of dot clock shift pulses to said second shift register, each pulse of said second series of dot clock shift pulses being delayed by substantially one-half said given dot period with respect to each pulse of said first series of dot clock shift pulses.

Claim 6

The system defined in claim 4, wherein the value of n is eight, whereby the first dimension of said first dot matrix is eight and the first dimension of said first dimension of said second dot matrix is sixteen.

Claim 7

The system defined in claim 5, wherein the second dimension of said first dot matrix is eight and the second dimension of said second dot matrix is sixteen, wherein said memory organization logic in response to the selection of said first dot matrix derives a symbol code portion of said symbol dot pattern address word containing m bits and derives a scan-line code portion of said symbol dot pattern address word containing three bits, and wherein said memory organization logic in response to the selection of said second dot matrix derives a symbol code portion of said symbol dot pattern address word containing (m-1) bits and derives a scan-line code portion of said symbol dot pattern address word containing four bits.

Claim 8

The system defined in claim 6, wherein the storage capacity of said character generator memory 1024 sixteen-bit words, and the value of m is seven, whereby said character generator memory can store two-hundred fifty-six symbols in 8 X 8 dot matrix form or 64 symbols in 16 X 16 dot matrix form.