US3928797A
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Circuit for converting a frequency into a binary number
Assignee: Robert Bosch GmbH
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Filing: 1974-06-25
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Granted: 1975-12-23
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Expires: 1994-06-25
Abstract
Abstract The frequency of a pulse sequence, such as pulses produced by a tachogenerator to measure the rate of rotation of a vehicle wheel or an engine shaft, is measured with a short response time by a circuit which is provided with pulses of the frequency to be measured and with timing pulses of a frequency much higher than the highest frequency to be measured. A downwards counter is reset to a maximum count value by a first pulse of the frequency to be measured and is caused to count down at a count value that varies hyperbolically with respect to time. The count result at the moment of the next pulse of the frequency to be measured gives the measurement of frequency as a binary number. During an initial portion of the count period, the count output for practical reasons is not hyperbolic. Therefore, if the final count is equal to or greater than half the initial maximum number, the scale is automatically shifted to count over two cycles of the frequency to be measured with reference to a different hyperbola with twice the slope at the same values of count, compared to the hyperbola used for the first measurement. Measurements are continually repeated, so that the output binary number changes as the frequency measured changes, with a short response time, even for low frequencies.
Inventors
- 👤 Uwe Kiencke
- 👤 Gunter Honig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:35
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/02; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/025; H; H03; H03M; H03M1/00; H03M1/12; H03M1/60
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
269 words
Circuit for converting a frequency into a binary number in response to a sequence of pulses of said frequency and to a sequence of clock pulses of a much higher frequency comprising: downward binary number counting means (40) arranged to be initially set and reset at a maximum count number by a reset signal and to count downwards from said number in response to counting pulses; count timing means responsive to said clock pulses for providing said counting means a count-versus-time characteristic that is substantially hyperbolic for a predetermined period of its downcounting operation, said count timing means being dependent on the momentary count output of said counting means and including decoding means (46) for detecting the values of count at which the counting rate should be reduced by a predetermined amount for provision of said hyperbolic characteristic and for generating a modifying signal determining a factor by which the frequency of said clock pulses is reducible; multiplying means (50) for reducing the frequency of said clock pulses by said factOr in response to said clock pulses and said modifying signal and for producing counting pulses for said counting means; registering means (30) for receiving the momentary count value in said counting means after counting down from said maximum count number for a predetermined integral number of periods of said frequency to be measured and for holding said count value for readout thereafter for at least one period of said frequency to be measured, and resetting means (22) for providing a reset signal to said counting means after a count value is received as aforesaid by said registering means.
Claim 2
Dependent Claim
269 words
Circuit for converting a frequency into a binary number in response to a sequence of pulses of said frequency and to a sequence of clock pulses of a much higher frequency comprising: downward binary number counting means (40) arranged to be initially set and reset at a maximum count number by a reset signal and to count downwards from said number in response to counting pulses; count timing means responsive to said clock pulses for providing said counting means a count-versus-time characteristic that is substantially hyperbolic for a predetermined period of its downcounting operation, said count timing means being dependent on the momentary count output of said counting means and including decoding means (46) for detecting the values of count at which the counting rate should be reduced by a predetermined amount for provision of said hyperbolic characteristic and for generating a modifying signal determining a factor by which the frequency of said clock pulses is reducible; multiplying means (50) for reducing the frequency of said clock pulses by said factOr in response to said clock pulses and said modifying signal and for producing counting pulses for said counting means; registering means (30) for receiving the momentary count value in said counting means after counting down from said maximum count number for a predetermined integral number of periods of said frequency to be measured and for holding said count value for readout thereafter for at least one period of said frequency to be measured, and resetting means (22) for providing a reset signal to said counting means after a count value is received as aforesaid by said registering means.
Claim 3
Dependent Claim
133 words
Circuit for converting a frequency into a binary number as defined in claim 1, in which said predetermined periods of said frequency to be measured in initially 1, and in which there are provided: scale shift means responsive to receipt by said registering means of a count value of at least half of said maximum count number for changing said predetermined number of periods to 2 for the next countdown from said maximum operation, said scale shift means also including means for modifying the operating characteristic of said decoding means to provide a different set of count values at which said decoding means is operable to change the counting rate of said counting means, and a different set of frequency reducing factors for said modifying signals by which said counting rate is changed.
Claim 4
Dependent Claim
48 words
Circuit for converting a frequency into a binary number as defined in claim 2, in which said scale shift means also includes means for changing said maximum count number for a succeeding count when said scale shift means operates to change said predetermined number of periods as aforesaid.
Claim 5
Dependent Claim
72 words
Circuit for converting a frequency into a binary number as defined in claim 1, in which means are provided for causing said registering means to receive the count value in said counting means upon the occurrence of the next clock pulse following a pulse of said frequency (f1) to be converted and for resetting said counting means upon the occurrence of the clock pulse next following the last previously mentioned clock pulse.
Claim 6
Dependent Claim
181 words
Circuit for converting a frequency into a binary number as defined in claim 2, in which said scale shift means comprises: a first AND-gate (12) having a first input (11) arranged to receive pulses of said frequency (f1) to be measured; a second AND-gate (15) having a first input (14) likewise arranged to receive pulses of said frequency (f1) to be measured; a J-K flipflop circuit (18) having its K input connected to receive pulses of said frequency (f1) to be measured and having its J input connected to the output of said second AND-gate (15) and its timing input connected to said clock frequency (f0) pulses, and also having its inverting output connected to a second input of said first AND-gate (12); the output (f2) of said first AND-gate (12) being made available as a timing signal to said registering means (30) for causing the latter to receive the momentary count of said downward counter (40), and a second input (16) of said second AND-gate (15) being connected to receive the most significant bit (MSB) of said registering means (30).
Claim 7
Dependent Claim
61 words
Circuit for converting a frequency into a binary number as set forth in claim 5, in which said output signal (f2) of said first AND-gate (12) is supplied to a D flipflop circuit arranged to operate in synchronism with said first mentioned clock frequency (f0) and having an output connected to a reset input (41) of said downward counting means (40).
Claim 8
Dependent Claim
44 words
Circuit for converting a frequency into a binary number as set forth in claim 5, in which the value of the most significant bit of said register (30) is made available to the portion of said scale shift means affecting said decoding means (46).
Claim 9
Dependent Claim
55 words
Circuit for converting a frequency into a binary number as set forth in claim 1, in which the value of the most signiFicant bit of said binary count output is supplied to the portion (60) of said scale shift means affecting the value of said maximum count number reset in said downward counting means (40).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-22 | 1979-06-23 | 1979-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-22 | 1983-06-23 | 1983-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-22 | 1987-06-23 | 1987-12-23 | $7700.00 | Window Closed / Lapsed |