US3924186A
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Staggered quadriphase differential encoder and decoder
Assignee: Raytheon Co
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Filing: 1974-02-07
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Granted: 1975-12-02
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Expires: 1994-02-07
Abstract
Abstract A differential encoder-decoder implementation for staggered quadriphase PSK modulation wherein a stream of digital data is interleaved into a first and a second channel, at staggered clock times, by the transitions in a clock signal and an inverted clock signal respectively. The clocked data signals in each channel are logically AND''ed to the channel associated clock signal and divided in rate by a common factor to provide the channel encoded signals. The encoded signals from the two channels are fed to individual modulators for modulating carrier signals in quadrature. The modulated quadrature carrier signals are combined into a staggered quadriphase differential PSK modulated signal which is transmitted to a receiver over a transmission path. The receiver detects and demodulates the received signal to provide two data streams. A decoder channel is provided for each data stream, wherein each data stream is decoded independently of the other. A deinterleaver receives the two decoded data streams and by utilizing clock signals, recovered from the bit timing in the received signal, places the data into a single stream of digital data which data stream corresponds to the stream of digital data received by the encoder.
Inventors
- 👤 Robert S Gordy
- 👤 David E Sanders
- 👤 Alfred T Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 09:36
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/233; H04L27/2332; H04L27/20; H04L27/2032; H04L27/2053; H04L27/206; H04L27/2067; H04L27/2078; H04L27/2082
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
271 words
An encoder and decoder for use in a digital data transmission system for the encoding and decoding of a digital data signal wherein said encoder comprises: a first and a second encoder channel wherein said digital data signal is alternately clocked thru said first and said second channel at staggered times by a clock signal and an inverted clock signal, respectively; means in each of said channels for providing the complement signal of the digital signal present at a channel input upon the occurrence of a transition in a channel associated clock signal; means in each of said channels for logically AND''ing the provided complement signal with the channel associated clock signal to provide an AND''ed signal; means in each of said channels for dividing said AND''ed signal by a common factor to provide a channel encoded signal; and wherein said decoder comprises: a first and a second decoder channel wherein the one channel encoded signal is applied to said first decoder channel and the other channel encoded signal is applied to said second decoder channel; means in each of said channels for delaying the respective channel encoded signal for a predetermined time interval; means in each of said decoder channels for combining the delayed channel encoded signal with the undelayed channel encoded signal to provide a partially decoded signal; means in each of said decoder channels for gating said partially decoded signal as a function of a channel associated clock signal to provide a channel data signal; and means for combining the channel data signal from each of said decoder channel gating means to provide a decoded digital data signal.
Claim 2
Dependent Claim
271 words
An encoder and decoder for use in a digital data transmission system for the encoding and decoding of a digital data signal wherein said encoder comprises: a first and a second encoder channel wherein said digital data signal is alternately clocked thru said first and said second channel at staggered times by a clock signal and an inverted clock signal, respectively; means in each of said channels for providing the complement signal of the digital signal present at a channel input upon the occurrence of a transition in a channel associated clock signal; means in each of said channels for logically AND''ing the provided complement signal with the channel associated clock signal to provide an AND''ed signal; means in each of said channels for dividing said AND''ed signal by a common factor to provide a channel encoded signal; and wherein said decoder comprises: a first and a second decoder channel wherein the one channel encoded signal is applied to said first decoder channel and the other channel encoded signal is applied to said second decoder channel; means in each of said channels for delaying the respective channel encoded signal for a predetermined time interval; means in each of said decoder channels for combining the delayed channel encoded signal with the undelayed channel encoded signal to provide a partially decoded signal; means in each of said decoder channels for gating said partially decoded signal as a function of a channel associated clock signal to provide a channel data signal; and means for combining the channel data signal from each of said decoder channel gating means to provide a decoded digital data signal.
Claim 3
Dependent Claim
25 words
The encoder and decoder according to claim 1 wherein said means for providing the complement signal of the digital data signal is a clocked flip-flop.
Claim 4
Dependent Claim
18 words
The encoder and decoder according to claim 1 wherein said means for logically AND''ing is a NOR gate.
Claim 5
Dependent Claim
55 words
The encoder and decoder according to claim 1 wherein said means for dividing is a clocked flip-flop having a clocking input for receiving said ANd''ed signal, a data input, and complementary outputs, said data input connected to one of said complementary outputs, said channel encoded signal being taken from the other of said complementary outputs.
Claim 6
Dependent Claim
67 words
The encoder and decoder according to claim 1 wherein said means for delaying the respective channel encoded signal is a clocked flip-flop having a clocking input for receiving a detected clock signal, a data input for receiving a respective channel encoded signal, and an output, the signal present at said output being the signal present at said data input during a transition of the detected clock signAl.
Claim 7
Dependent Claim
28 words
The encoder and decoder according to claim 1 wherein said means for combining the delayed channel encoded signal with the undelayed channel encoded signal is an EXCLUSIVE-OR gate.
Claim 8
Dependent Claim
21 words
The encoder and decoder according to claim 1 wherein said means for gating said partially decoded signals is an AND gate.
Claim 9
Dependent Claim
21 words
The encoder and decoder according to claim 1 wherein said means for combining the channel data signals is an OR gate.
Claim 10
Dependent Claim
185 words
An encoder for use in a digital data transmission system for the encoding of a digital data signal wherein said digital data signal is comprised of successive bit periods having transitions between first and second levels, said encoder comprising: first and second encoder channels adapted to receive said digital data signal and first and second train of pulses, said first and second train of pulses comprising pulses each having a width equal to the bit period of said digital data signal, with the second train of pulses being inverted from said first train of pulses; means for interleaving said digital data signal between said first and said second encoder channels in response to said first and said second train of clock pulses, respectively, at a rate corresponding to one-half of the data bit period; means in each of said channels for logically AND''ing the complement of the interleaved digital data signal with the channel associated clock signal to provide an AND''ed signal; means in each of said channels for dividing said AND''ed signal in rate by a common factor to provide the channel encoded signals.
Claim 11
Dependent Claim
185 words
An encoder for use in a digital data transmission system for the encoding of a digital data signal wherein said digital data signal is comprised of successive bit periods having transitions between first and second levels, said encoder comprising: first and second encoder channels adapted to receive said digital data signal and first and second train of pulses, said first and second train of pulses comprising pulses each having a width equal to the bit period of said digital data signal, with the second train of pulses being inverted from said first train of pulses; means for interleaving said digital data signal between said first and said second encoder channels in response to said first and said second train of clock pulses, respectively, at a rate corresponding to one-half of the data bit period; means in each of said channels for logically AND''ing the complement of the interleaved digital data signal with the channel associated clock signal to provide an AND''ed signal; means in each of said channels for dividing said AND''ed signal in rate by a common factor to provide the channel encoded signals.
Claim 12
Dependent Claim
16 words
The encoder according to claim 9 wherein said means for logically AND''ing is a NOR gate.
Claim 13
Dependent Claim
56 words
The encoder according to claim 9 wherein said means for dividing said AND''ed signal is a clocked flip-flop having a clocking input for receiving said AND''ed signal, a data input, and complementary outputs, said data input connected to one of said complementary outputs, said channel encoded signal being taken from the other of said complementary outputs.
Claim 14
Dependent Claim
18 words
The encoder according to claim 9 wherein said means for dividing said AND''ed signal is a divide-by-two means.
Claim 15
Dependent Claim
130 words
A decoder for use in a digital data transmission system for the decoding of channel encoded signals comprising: a first decoder channel means for comparing a previously received portion of a channel encoded signal against a successively received portion of the received channel signal to provide a first difference signal; a second decoder means for comparing a previously received portion of a channel encoded signal against a successively received portion of the channel encoded signal to provide a second difference signal; a first and a second gating means for gating said first and said second difference signals in response to a clock signal and an inverted clock signal, respectively; and gating means for adding the gated signals from said first and said second gating means to provide a decoded signal.
Claim 16
Dependent Claim
130 words
A decoder for use in a digital data transmission system for the decoding of channel encoded signals comprising: a first decoder channel means for comparing a previously received portion of a channel encoded signal against a successively received portion of the received channel signal to provide a first difference signal; a second decoder means for comparing a previously received portion of a channel encoded signal against a successively received portion of the channel encoded signal to provide a second difference signal; a first and a second gating means for gating said first and said second difference signals in response to a clock signal and an inverted clock signal, respectively; and gating means for adding the gated signals from said first and said second gating means to provide a decoded signal.
Claim 17
Dependent Claim
17 words
The decoder according to claim 13 wherein said first and said second gating means are AND gates.
Claim 18
Dependent Claim
16 words
The decoder according to claim 13 wherein said gating means for adding is an OR gate.
Claim 19
Dependent Claim
210 words
An encoder for use in a digital data transmission system for the encoding of a digital data signal wherein said digital data signal is comprised of successive bit periods having transitions between first and second levels, said encoder comprising: first and second encoder channels adapted to receive said digital data signal and a first and second train of pulses, respectively, wherein said first and second train of pulses are comprised of pulses having a width equal to the bit period of said digital data signal, with the second train of pulses being inverted from said first train of pulses; said first and said second encoder channels each comprised of; a first clocked flip-flop having a clocking input for receiving the channel associated train of clock pulses, a data input for receiVing said digital data signal, and complementary outputs; a NOR gate having one input connected to a complementary output of said first clocked flip-flop and another input connected to receive the channel associated train of clock pulses; a second clocked flip-flop, having a clocking input connected to the output of said NOR gate, a data input, and complementary outputs, one of said complementary outputs connected to said data input, the other of said complementary outputs containing a channel encoded signal.
Claim 20
Dependent Claim
210 words
An encoder for use in a digital data transmission system for the encoding of a digital data signal wherein said digital data signal is comprised of successive bit periods having transitions between first and second levels, said encoder comprising: first and second encoder channels adapted to receive said digital data signal and a first and second train of pulses, respectively, wherein said first and second train of pulses are comprised of pulses having a width equal to the bit period of said digital data signal, with the second train of pulses being inverted from said first train of pulses; said first and said second encoder channels each comprised of; a first clocked flip-flop having a clocking input for receiving the channel associated train of clock pulses, a data input for receiVing said digital data signal, and complementary outputs; a NOR gate having one input connected to a complementary output of said first clocked flip-flop and another input connected to receive the channel associated train of clock pulses; a second clocked flip-flop, having a clocking input connected to the output of said NOR gate, a data input, and complementary outputs, one of said complementary outputs connected to said data input, the other of said complementary outputs containing a channel encoded signal.
Claim 21
Dependent Claim
174 words
A decoder for use in a digital data transmission system for the decoding of the two encoded channel signals resulting from the demodulation of a staggered quadriphase differential encoded channel signal comprising: a first and a second decoder channel wherein each of said channels is comprised of; a clocked flip-flop having a clocking input for receiving the channel associated recovered data clock signal, a data input for receiving the encoded channel signal, and complementary outputs; an EXCLUSIVE-OR gate, having one input connected to the non-inverting output of said flip-flop and the other input connected to the data input of said flip-flop; an AND gate having one input connected to the output of said EXCLUSIVE-OR gate and the other input connected to the clocking input of said flip-flop; and an OR gate having one input connected to the output of the AND gate of said first channel and the other input connected to the output of the AND gate of said second channel, with the output signal from said OR gate being the decoded signal.
Claim 22
Dependent Claim
174 words
A decoder for use in a digital data transmission system for the decoding of the two encoded channel signals resulting from the demodulation of a staggered quadriphase differential encoded channel signal comprising: a first and a second decoder channel wherein each of said channels is comprised of; a clocked flip-flop having a clocking input for receiving the channel associated recovered data clock signal, a data input for receiving the encoded channel signal, and complementary outputs; an EXCLUSIVE-OR gate, having one input connected to the non-inverting output of said flip-flop and the other input connected to the data input of said flip-flop; an AND gate having one input connected to the output of said EXCLUSIVE-OR gate and the other input connected to the clocking input of said flip-flop; and an OR gate having one input connected to the output of the AND gate of said first channel and the other input connected to the output of the AND gate of said second channel, with the output signal from said OR gate being the decoded signal.
References Cited (Backward Citations)
US3349330A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-12-01 | 1979-06-02 | 1979-12-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-12-01 | 1983-06-02 | 1983-12-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-12-01 | 1987-06-02 | 1987-12-02 | $7700.00 | Window Closed / Lapsed |