Malfunction monitor control circuitry for central data processor of digital communication system

Claim 1

In a data processing system having first and second central data processors each operating synchronously and including processing circuits and maintenance circuits, said system being adapted wherein only one of said processors is active at one time and the other is standby, and further including first and second storage means, each provided with its own bus and adapted for selective communication with said data processors, said data processors each including a storage register for said storage means, the improvement comprising: timing generator circuit means for generating at least two separate sequential mutually exclusive timing level signals; malfunction monitor circuit means in each of said central processors for detecting and isolating malfunctions in said system and including: match network circuit means receiving first sets of data signals responsive to said mutually exclusive timing level signals from the data processing circuits of its own central processor and receiving second sets of data signals responsive to said mutually exclusive timing level signals from the data processing circuits of the other central processor for comparing said first and second sets of data signals and generating mismatch error level signals when said first and second sets of data signals do not match; first malfunction analysis circuit means responsive to said mismatch error signals, and said mutually exclusive, timing level signals for generating output signals representative of a suspected circuit of said system causing the mismatch; and parity network circuit means receiving signals transmitted to and received from said external storage means for checking the parity thereof and for generating parity error signals in response to a detected parity error; and wherein said malfunction analysis circuit is further responsive to said parity error signals.