US3916380A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-computer multiple data path hardware exchange system
Assignee: National Aeronautics and Space Administration
•
Filing: 1974-11-06
•
Granted: 1975-10-28
•
Expires: 1994-11-06
Abstract
Abstract A switch controller in a multi-computer processing system functions to establish a data path between any two computers in the system and maintain that data path, without interference, while establishing other independent unidirectional data paths with other pairs of computers. All computers in the system are continuously and rapidly scanned for a request-to-send signal. Those computers that are already engaged in data transmission are leap-frogged by the scanning mechanism. When a request-to-send signal is detected by a particular scanning mechanism, that scanning mechanism stops at the computer generating the request, to provide for an interconnection between the requesting sender and the intended receiver. If during this interconnection phase, it is determined that the intended receiver is occupied, the interconnection is prevented from being completed and the scanning mechanism is instructed to resume scanning of the computers for another request-to-send signal.
Inventors
- 👤 James C Administrator Fletcher
- 👤 Tage O Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 21:07
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
143 words
In a multi-computer processor system wherein a plurality of computers generate request-to-send signals indicating a desire to be connected to another computer or device over one of N independent unidirectional data paths, a multiple data path hardware exchange system, comprising: N scanning means, each of said scanning means connecting and disconnecting a first end of a data path from the output lines of each said computers; sequencing means for directing the sequential connecting and disconnecting of each said N scanning means, said sequencing means responding to a request-to-send signal from a particular computer by maintaining a scanning means connected to said particular computer, said sequencing means causing all other scanning means to leap-frog the connected scanning means; and N distribution means, each of said distribution means connecting the second end of the data path to the input lines of another computer or device.
Claim 2
Dependent Claim
143 words
In a multi-computer processor system wherein a plurality of computers generate request-to-send signals indicating a desire to be connected to another computer or device over one of N independent unidirectional data paths, a multiple data path hardware exchange system, comprising: N scanning means, each of said scanning means connecting and disconnecting a first end of a data path from the output lines of each said computers; sequencing means for directing the sequential connecting and disconnecting of each said N scanning means, said sequencing means responding to a request-to-send signal from a particular computer by maintaining a scanning means connected to said particular computer, said sequencing means causing all other scanning means to leap-frog the connected scanning means; and N distribution means, each of said distribution means connecting the second end of the data path to the input lines of another computer or device.
Claim 3
Dependent Claim
44 words
The multiple data path hardware exchange system of claim 1 wherein each of said N scanning means comprises X, Y:1 multiplexers, X being the number of output lines per data path and Y being the number of computers and devices in said processor system.
Claim 4
Dependent Claim
63 words
The multiple data path hardware exchange system of claim 1 wherein said sequencing means comprises: means for generating inbound addresses for each of said N scanning means; means for detecting when a particular scanning means is quiescent at a particular address; and means for directing said inbound address generating means to leap-frog the inbound address at which said particular scanning means is quiescent.
Claim 5
Dependent Claim
30 words
The multiple data path hardware exchange system of claim 3 wherein said means for generating inbound addresses comprises: N sequencers, each sequencer generating an address for its respective scanning means.
Claim 6
Dependent Claim
40 words
The multiple data path hardware exchange system of claim 4 wherein said detecting means comprises: a plurality of comparators, each comparator comparing the next address to be generated by a first sequencer with the present address of a second sequencer.
Claim 7
Dependent Claim
21 words
The multiple data path hardware exchange system of claim 3 wherein said leap-frog directing means comprises: a leap-frog constant store means.
Claim 8
Dependent Claim
53 words
The multiple data path hardware exchange system of claim 3 wherein said means for generating inbound addresses comprises N sequencers, each sequencer comprising: an address hold register; and a full adder receiving the output of said address register as a first input and supplying its output to the input of said hold register.
Claim 9
Dependent Claim
43 words
The multiple data path hardware exchange system of claim 7 wherein said detecting means comprises: a plurality of comparators, each comparator comparing the output of said full adder in a first sequencer with the output of said hold register in a second sequencer.
Claim 10
Dependent Claim
59 words
The multiple data path hardware exchange system of claim 8 wherein said directing means comprises N directing means, each directing means comprising: a storage means containing a plurality of leap-frog constants; and means responsive to a particular said comparator for selecting a leap-frog constant from said storage means and supplying it to said full adder as a second input.
Claim 11
Dependent Claim
54 words
The multiple data path hardware exchange system of claim 7 wherein said directing means comprises: a storage means containing a pluralitY of leap-frog constants; and means responsive to a particular said comparator for selecting a leap-frog constant from said storage means and supplying it to said full adder in one of said N sequencers.
Claim 12
Dependent Claim
59 words
The multiple data path hardware exchange system of claim 3 further comprising: an outbound address generating means responding to a destination code from a computer for generating outbound addresses for each of said N distribution means; and an inbound/outbound address comparator means for comparing addresses from said outbound address generating means and address from said inbound address generating means.
Claim 13
Dependent Claim
52 words
The multiple data path hardware exchange system of claim 11 wherein said outbound address generating means comprises: a register means for receiving a destination code from a computer by way of said scanning means; and a memory means responsive to the destination code in said register means for generating an outbound address.
Claim 14
Dependent Claim
65 words
The multiple data path hardware exchange system of claim 11 wherein said inbound/outbound address comparator means comprises: a plurality of binary comparator means, a first comparator means comparing the present outbound address with an inbound address for one of said N scanning means; and a second comparator means comparing the present outbound address with a previous outbound address generated by said outbound address generating means.
Claim 15
Dependent Claim
37 words
The multiple data path hardware exchange system of claim 13 further comprising: means for routing indications of a match from said plurality of comparator means in said inbound/outbound address comparator means to respective inbound address generating means.
Claim 16
Dependent Claim
44 words
The multiple data path hardware exchange system of claim 1 wherein each of said N distribution means comprises: X, 1:Y demultiplexers, X being the number of input lines per data path and Y being the number of computers and devices in said processor system.
Claim 17
Dependent Claim
160 words
In a multi-computer processor system wherein a plurality of computers generate request-to-send signals indicating a desire to be connected to another computer or device over one of N independent unidirectional paths made available by N scanning means and N distribution means, an interchange control mechanisms for regulating said scanning means and distributing means, comprising: timing control logic responsive to request-to-send signals from said plurality of computers, transmitted to said timing control logic by said N scanning means; scanning control means responsive to request-to-send signals received from said N scanning means for controlling the movement of said N scanning means by generating inbound addresses for said N scanning means; an outbound address generator for receiving an address code from a computer that has had its request-to-send signal acknowledged by said timing control logic, and generating on outbound address for a particular one of said N distribution means; and comparator means for receiving inbound addresses from said address generator and comparing them.
Claim 18
Dependent Claim
160 words
In a multi-computer processor system wherein a plurality of computers generate request-to-send signals indicating a desire to be connected to another computer or device over one of N independent unidirectional paths made available by N scanning means and N distribution means, an interchange control mechanisms for regulating said scanning means and distributing means, comprising: timing control logic responsive to request-to-send signals from said plurality of computers, transmitted to said timing control logic by said N scanning means; scanning control means responsive to request-to-send signals received from said N scanning means for controlling the movement of said N scanning means by generating inbound addresses for said N scanning means; an outbound address generator for receiving an address code from a computer that has had its request-to-send signal acknowledged by said timing control logic, and generating on outbound address for a particular one of said N distribution means; and comparator means for receiving inbound addresses from said address generator and comparing them.
Claim 19
Dependent Claim
71 words
The interchange control mechanism of claim 16 wherein said scanning control means comprises: N sequencing means, one for each of said N scanning means, for generating inbound addresses for their respective scanning means; and a plurality of comparator means, a first comparator comparing the next address to be generated by a first of said N sequencing means with the address presently being generated by a second of said N sequencing means.
Claim 20
Dependent Claim
45 words
The interchange control mechanism of claim 17 wherein said N sequencing means each comprises: an address hold register; and a binary full adder receiving the output of said address register as a first input and supplying its output to the input of said hold register.
Claim 21
Dependent Claim
50 words
The interchange control mechanism of claim 18 wherein said N sequencing means each further comprises: storage means containing a plurality of biNary leap-frog constants; and selector means responsive to said comparator means for selecting one of said leap-frog constants and supplying it to said full adder as a second input.
Claim 22
Dependent Claim
60 words
The interchange control mechanism of claim 16 wherein said comparator means comprises: a plurality of binary comparator means, a first comparator means comparing the present outbound address with an inbound address for one of said N scanning means; and a second comparator means comparing the present outbound address with a previous outbound address generated by said outbound address generating means.
Claim 23
Dependent Claim
28 words
The interchange control mechanism of claim 20 further comprising: means for routing indications of a match from said plurality of comparator means to respective said scanning control means.
Claim 24
Dependent Claim
81 words
A binary address generator for simultaneously stepping a plurality of scanning devices, comprising: a plurality of sequencers, equal in number to said scanning devices, each sequencer generating a sequence of multiple bit codes; and a plurality of comparators connected between said plurality of sequencers and comparing the multiple bit codes from said plurality of sequencers, a first comparator comparing the multiple bit code to be released by a first sequencer with the multiple bit code being released by a second sequencer.
Claim 25
Dependent Claim
81 words
A binary address generator for simultaneously stepping a plurality of scanning devices, comprising: a plurality of sequencers, equal in number to said scanning devices, each sequencer generating a sequence of multiple bit codes; and a plurality of comparators connected between said plurality of sequencers and comparing the multiple bit codes from said plurality of sequencers, a first comparator comparing the multiple bit code to be released by a first sequencer with the multiple bit code being released by a second sequencer.
Claim 26
Dependent Claim
19 words
The binary address generator of claim 22 wherein said first comparator is enabled whenever said second sequencer is disabled.
Claim 27
Dependent Claim
31 words
The binary address generator of claim 22 further comprising: means responsive to a compare indication from a comparator for changing the sequence of a particular sequencer of said plurality of sequencers.
Claim 28
Dependent Claim
33 words
The binary address generator of claim 24 wherein said sequence changing means comprises: storage means containing a plurality of binary bit codes; and selector means for selecting one of said binary bit codes.
Claim 29
Dependent Claim
52 words
The binary address generator of claim 22 wherein each sequencer of said plurality of sequencers comprises: a hold register for a plurality of binary bits; and a full adder having a first input connected to the output of said hold register and its output connected to the input of said hold register.
Claim 30
Dependent Claim
39 words
The binary address generator of claim 26 further comprising: storage means containing a plurality of binary bit codes; and selector means for selecting one of said binary codes and supplying it as a second input to said full adder.
Claim 31
Dependent Claim
36 words
The binary address generator of claim 27 wherein said selector means responds to a compare indication from one of said plurality of comparators for selecting a particular binary code to be supplied to said full adder.
Claim 32
Independent Claim
54 words
A method for simultaneously stepping a plurality of scanning devices, comprising: generating a separate sequence of multiple bit codes for each one of said plurality of scanning devices; and comparing the multiple bit code to be generated for a first scanning device with the multiple bit code being generated for a second scanning device.
Claim 33
Independent Claim
54 words
A method for simultaneously stepping a plurality of scanning devices, comprising: generating a separate sequence of multiple bit codes for each one of said plurality of scanning devices; and comparing the multiple bit code to be generated for a first scanning device with the multiple bit code being generated for a second scanning device.
Claim 34
Dependent Claim
28 words
The method of claim 29, further comprising: changing the sequence being generated for a particular scanning device in response to a compare indication resulting from said comparing step.
References Cited (Backward Citations)
US3366849A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-10-27 | 1979-04-28 | 1979-10-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-10-27 | 1983-04-28 | 1983-10-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-10-27 | 1987-04-28 | 1987-10-28 | $7700.00 | Window Closed / Lapsed |