Memory having non-fixed relationships between addresses and storage locations

Claim 2

A multi-mode memory comprising a first plurality of storage locations each having a respective access address, a second plurality of storage locations each having a respective access address and at least some of which are used for containing the access addresses of some of said storage locations in said first plurality, a plurality of data lines, means for transferring data between said data lines and either a selected one of the storage locations in said second plurality or a selected one of the storage locations in said first plurality having a derived access address, a plurality of address lines for receiving thereon memory addresses having a plurality of bits therein, means for verifying that a received memory address on said address lines is contained within one of several predetermined groups of memory addresses, and means responsive to the operation of said verifying means for deriving the access address of a selected storage location in either said first or said second plurality for use by said data transferring means, said deriving means including means for identifying from a received memory address a storage location in said second plurality and for deriving the access address of a selected storage location in said first plurality of performing a predetermined operation on the access address contained in the identified storage location in accordance with the values of at least some of the bits in the received memory address responsive to the received memory address being contained in at least one of said predetermined groups, said deriving means operating in one of several different modes in accordance with which predetermined group of memory addresses contains the received memory address.

Claim 3

A memory in accordance with claim 1 wherein said deriving means performs a different predetermined operation on an access address in accordance with which respective predetermined group of memory addresses contains the received memory address.

Claim 4

A memory in accordance with claim 1 wherein one of the modes of operation is a direct mode in which said deriving means derives the access address of a selected storage location in said first plurality by translating each received memory address within one of said predetermined groups by a preselected amount.

Claim 5

A memory in accordance with claim 3 further including means for adjusting the preselected amount by which each received memory address is translated to derive the access address of a storage location in said first plurality when said deriving means operates in said direct mode.

Claim 6

A memory in accordance with claim 3 further including means for establishing a set of contiguous memory addresses each of which when received results in said deriving means operating in said direct mode.

Claim 7

A memory in accordance with claim 1 wherein one of the modes of operation is a mapping mode in which said deriving means derives the access address of a selected storage location in said first plurality when the received memory address is contained within a predetermined mapping group, said mapping group including several memory address pages with each of said memory address pages being associated with a respective one of the storage locations in said second plurality, each of said respective storage locations in said second plurality containing the starting access address of a corresponding page of storage locations in said first plurality, said deriving means operating in the mapping mode to arithmetically combine the access address in that one of said storage locations in said second plurality which is associated with the memory address page which contains the received memory address with at least some of the bits in the received memory address to derive the access address of a selected storage location in said first plurality.

Claim 8

A memory in accordance with claim 6 wherein said at least some of the bits in the received memory address represent the difference between the received memory address and the starting memory address of the memory address page which contains the received memory address.

Claim 9

A memory in accordance with claim 6 further including means for controlling the storage of a new page starting access address which appears on said data lines in a storage location in said second plurality when the received memory address is contained within a special predetermined group, said deriving means including means for deriving the access address of a selected storage location in said second plurality from less than all of the bits in a received memory address which is contained within said special predetermined group.

Claim 10

A memory in accordance with claim 6 further including means for setting a number of contiguous memory address pages in said mapping group, a memory address in each of which when received results in said deriving means operating in said mapping mode.

Claim 11

A memory in accordance with claim 1 wherein one of the modes of operation is a special mode in which said deriving means derives the access address of a selected storage location in said second plurality when the received memory address is contained within a special predetermined group, said deriving means including means for deriving the access address of a selected storage location in said second plurality from at least some of the bits in a received memory address which is contained within said special predetermined group.

Claim 12

A memory in accordance with claim 10 further including means for setting a number of contiguous memory addresses which are contained in said special predetermined group.

Claim 13

A memory in accordance with claim 1 wherein one of the modes of operation is a stacking mode in which said deriving means derives the access address of a storage location in said first plurality when the received memory address is contained within a predetermined stacking group, said stacking group including a plurality of sub-groups the memory addresses in each of which are all associated with a respective one of the storage locations in said second plurality, each of said respective storage locations in said second plurality containing the respective access address of a storage location in a respective buffer area in said first plurality, said deriving means operating in the stacking mode to derive the access address of a storage location in said first plurality by performing a predetermined operation on the access address contained in the respective storage location in said second plurality which is associated with the received memory address in accordance with the values of less than all of the bits in the received memory address.

Claim 14

A memory in accordance with claim 12 wherein responsive to the receipt of at least one of the memory addresses in each of said sub-groups said deriving means modifies the access address contained in the associated storage location in said second plurality by a predetermined amount to derive the access address of a storage location in said first plurality.

Claim 15

A memory in accordance with claim 13 further including means for storing the modified access address in its previous storage location in said second plurality.

Claim 16

A memory in accordance with claim 13 wherein responsive to the receipt of at least one of the memory addresses in each of said sub-groups said deriving means decrements the access address contained in the associated storage location in said second plurality by 1.

Claim 17

A memory in accordance with claim 13 wherein responsive to the receipt of at least one Of the memory addresses in each of said sub-groups said deriving means decrements the access address contained in the associated storage location in said second plurality by 2.

Claim 18

A memory in accordance with claim 13 wherein responsive to the receipt of at least one of the memory addresses in each of said sub-groups the access address which is modified is used by said data transferring means and is left unchanged in its respective storage location in said second plurality.

Claim 19

A memory in accordance with claim 17 wherein responsive to the receipt of at least one of the memory addresses in each of said sub-groups the access address which is modified and used by said data transferring means is decremented by 1.

Claim 20

A memory in accordance with claim 17 wherein responsive to the receipt of at least one of the memory addresses in each of said sub-groups the access address which is modified and used by said data transferring means is decremented by 2.

Claim 21

A memory in accordance with claim 12 wherein responsive to the receipt of at least one of the memory addresses in each of said sub-groups said deriving means retrieves the access address contained in the associated storage location in said second plurality to derive the access address of a storage location in said first plurality and thereafter modifies the retrieved access address by a predetermined amount and stores the modified retrieved access address in its previous storage location in said second plurality.

Claim 22

A memory in accordance with claim 20 wherein the derived access address is made equal to the retrieved access address.

Claim 23

A memory in accordance with claim 20 wherein responsive to the receipt of at least one of the memory addresses in each of said sub-groups the retrieved access address contained in the associated storage location in said second plurality is modified by incrementing it by 1.

Claim 24

A memory in accordance with claim 20 wherein responsive to the receipt of at least one of the memory addresses in each of said sub-groups the retrieved access address contained in the associated storage location in said second plurality is modified by incrementing it by 2.

Claim 25

A memory in accordance with claim 12 further including means for controlling the storage of new access addresses which appear on said data lines in particular storage locations in said second plurality which are associated with received memory addresses contained in a special predetermined group, and means for identifying such a particular storage location in said second plurality from at least some of the bits in a received memory address which is contained within said special predetermined group.

Claim 26

A memory in accordance with claim 12 further including means for setting the successive memory addresses in said stacking group, a memory address in each of which when received results in said deriving means operating in said stacking mode.

Claim 27

A memory in accordance with claim 1 further including a plurality of storage means, and means responsive to the receipt of a predetermined memory address on said address lines for controlling the transfer of data from said data lines to said plurality of storage means.

Claim 28

A memory in accordance with claim 26 further including means responsive to data stored in said plurality of storage means for selectively enabling and disabling the operation of said deriving means in some of said several modes.

Claim 29

A memory in accordance with claim 1 further including means for selectively changing said predetermined operation performed by said deriving means responsive to a received memory address being contained in said at least one predetermined group.

Claim 30

A memory in accordance with claim 1 wherein at least two of said predetermined groups of memory addresses are adjustable and can overlap, and further including means for controlling a priority sequence with respect to the mode in which said deriving means is operated in the event a received memory address iS contained in at least two different ones of said predetermined groups.

Claim 31

A memory in accordance with claim 1 wherein memory addresses and data are received on said plurality of address and data lines from two sources, and further including means for delaying a data transfer operation in accordance with the memory address and data received from one source until after the completion of a data transfer operation which is in progress in accordance with the memory address and data received from the other source.

Claim 32

A memory for operating in a mapping mode comprising a first plurality of storage locations each having a respective access address, a second plurality of storage locations each having a respective access address, a plurality of data lines, means for transferring data between said data lines and either a selected one of the storage locations in said second plurality or a selected one of the storage locations in said first plurality having a derived access address, a plurality of address lines for receiving thereon memory addresses having a plurality of bits therein, some of said memory addresses being contained in a set of pages with all of the memory addresses in each of said pages being associated with the same respective one of the storage locations in said second plurality, others of said memory addresses being contained in a special group with each memory address therein being associated with a respective one of the storage locations in said second plurality, at least some of the storage locations in said second plurality containing the starting access addresses of pages of storage locations in said first plurality which correspond to the respective pages of memory addresses associated with said at least some storage locations in said second plurality, first means for deriving from a received memory address which is contained in said special group the access address of a selected storage location in said second plurality for use by said data transferring means, and second means for deriving from a received memory address which is contained in one of said pages the access address of a selected storage location in said first plurality for use by said data transferring means by combining the page starting access address contained in the associated storage location in said second plurality with at least some of the bits in the received memory address.

Claim 33

A memory for operating in a mapping mode comprising a first plurality of storage locations each having a respective access address, a second plurality of storage locations each having a respective access address, a plurality of data lines, means for transferring data between said data lines and either a selected one of the storage locations in said second plurality or a selected one of the storage locations in said first plurality having a derived access address, a plurality of address lines for receiving thereon memory addresses having a plurality of bits therein, some of said memory addresses being contained in a set of pages with all of the memory addresses in each of said pages being associated with the same respective one of the storage locations in said second plurality, others of said memory addresses being contained in a special group with each memory address therein being associated with a respective one of the storage locations in said second plurality, at least some of the storage locations in said second plurality containing the starting access addresses of pages of storage locations in said first plurality which correspond to the respective pages of memory addresses associated with said at least some storage locations in said second plurality, first means for deriving from a received memory address which is contained in said special group the access address of a selected storage location in said second plurality for use by said data transferring means, and second means for deriving from a received memory address which is contained in one of said pages the access address of a selected storage location in said first plurality for use by said data transferring means by combining the page starting access address contained in the associated storage location in said second plurality with at least some of the bits in the received memory address.

Claim 34

A memory in accordance with claim 31 wherein said second deriving means arithmetically combines said page starting access address with at least some of the bits in the received memory address to derive the access address of said selected storage location in said first plurality.

Claim 35

A memory in accordance with claim 32 wherein said at least some of the bits in the received memory address represent the difference between the received memory address and the starting memory address of the memory address page which contains the received memory address.

Claim 36

A memory in accordance with claim 33 wherein said first deriving means derives the access address of a selected storage location in said second plurality from at least some of the bits in a received memory address which is contained within said special group.

Claim 37

A memory in accordance with claim 34 further including means for setting the number of pages which contain memory addresses which when received result in the operation of said second deriving means.

Claim 38

A memory in accordance with claim 31 wherein said first deriving means derives the access address of a selected storage location in said second plurality from at least some of the bits in a received memory address which is contained within said special group.

Claim 39

A memory in accordance with claim 36 further including means for setting the number of pages which contain memory addresses which when received result in the operation of said second deriving means.

Claim 40

A memory in accordance with claim 31 further including means for setting the number of pages which contain memory addResses which when received result in the operation of said second deriving means.

Claim 41

A memory in accordance with claim 31 wherein memory addresses and data are received on said plurality of address and data lines from two sources, and further including means for delaying a data transfer operation in accordance with the memory address and data received from one source until after the completion of a data transfer operation which is in progress in accordance with the memory address and data received from the other source.

Claim 42

A memory for operating in a stacking mode comprising a first plurality of storage locations each having a respective access address, a second plurality of storage locations each having a respective access address, a plurality of data lines, means for transferring data between said data lines and either a selected one of the storage locations in said second plurality or a selected one of the storage locations in said first plurality having a derived access address, a plurality of address lines for receiving thereon memory addresses having a plurality of bits therein, some of said memory addresses being contained in respective groups with all of the memory addresses in each of said groups being associated with the same respective one of the storage locations in said second plurality, others of said memory addresses being contained in a special set with each memory address therein being associated with a respective one of the locations in said second plurality, at least some of the storage locations in said second plurality containing the access addresses of storage locations in said first plurality, first means for deriving from a received memory address which is contained in said special set the access address of a selected storage location in said second plurality for use by said data transferring means, and second means for deriving from a received memory address which is contained in one of said groups the access address of a selected storage location in said first plurality for use by said data transferring means by performing a predetermined operation on the access address contained in the associated storage location in said second plurality in accordance with the values of at least some of the bits in the received memory address.

Claim 43

A memory for operating in a stacking mode comprising a first plurality of storage locations each having a respective access address, a second plurality of storage locations each having a respective access address, a plurality of data lines, means for transferring data between said data lines and either a selected one of the storage locations in said second plurality or a selected one of the storage locations in said first plurality having a derived access address, a plurality of address lines for receiving thereon memory addresses having a plurality of bits therein, some of said memory addresses being contained in respective groups with all of the memory addresses in each of said groups being associated with the same respective one of the storage locations in said second plurality, others of said memory addresses being contained in a special set with each memory address therein being associated with a respective one of the locations in said second plurality, at least some of the storage locations in said second plurality containing the access addresses of storage locations in said first plurality, first means for deriving from a received memory address which is contained in said special set the access address of a selected storage location in said second plurality for use by said data transferring means, and second means for deriving from a received memory address which is contained in one of said groups the access address of a selected storage location in said first plurality for use by said data transferring means by performing a predetermined operation on the access address contained in the associated storage location in said second plurality in accordance with the values of at least some of the bits in the received memory address.

Claim 44

A memory in accordance with claim 40 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said second deriving means uses the access address contained in the associated storage location in said second plurality as the access address of a storage location in said first plurality.

Claim 45

A memory in accordance with claim 41 further including means for modifying by a predetermined amount the access address used by said data transferring means and for storing the modified access address in its previous storage location in said second plurality.

Claim 46

A memory in accordance with claim 42 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said second deriving means increments the access address contained in the associated storage location in said second plurality by 1.

Claim 47

A memory in accordance with claim 42 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said second deriving means increments the access address contained in the associated storage location in said second plurality by 2.

Claim 48

A memory in accordance with claim 40 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said second deriving means increments the access address contained in the associated storage location in said second plurality by 1.

Claim 49

A memory in accordance with claim 40 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said second deriving means increments the access address contained in the associated storage location in said second plurality by 2.

Claim 50

A memory in accordance with claim 40 whErein responsive to the receipt of at least one of the memory addresses in each of said groups said second deriving means retrieves the access address contained in the associated storage location in said second plurality and modifies the retrieved access address by a predetermined amount to derive an access address of a storage location in said first plurality.

Claim 51

A memory in accordance with claim 47 wherein the access address which is modified is thereafter used by said data transferring means, and further including means for storing the modified address in its previous storage location in said second plurality.

Claim 52

A memory in accordance with claim 48 wherein responsive to the receipt of at least one of the memory addresses in each of said groups the retrieved access address contained in the associated storage location in said second plurality is modified by decrementing it by 1.

Claim 53

A memory in accordance with claim 48 wherein responsive to the receipt of at least one of the memory addresses in each of said groups the retrieved access address contained in the associated storage location in said second plurality is modified by decrementing it by 2.

Claim 54

A memory in accordance with claim 40 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said second deriving means retrieves the access address from the associated storage location in said second plurality and modifies it by a predetermined amount to derive the access address of a storage location in said first plurality, the access address in said associated storage location in said second plurality being left unchanged.

Claim 55

A memory in accordance with claim 51 wherein responsive to the receipt of at least one of the memory addresses in each of said groups the access address which is retrieved and modified is decremented by 1.

Claim 56

A memory in accordance with claim 51 wherein responsive to the receipt of at least one of the memory addresses in each of said groups the access address which is retrieved and modified is decremented by 2.

Claim 57

A memory in accordance with claim 40 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said second deriving means decrements the access address contained in the associated storage location in said second plurality by 1.

Claim 58

A memory in accordance with claim 40 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said second deriving means decrements the access address contained in the associated storage location in said second plurality by 2.

Claim 59

A memory in accordance with claim 40 further including means for setting the memory addresses contained in said respective groups.

Claim 60

A memory in accordance with claim 40 wherein memory addresses and data are received on said plurality of address and data lines from two sources, and further including means for delaying a data transfer operation in accordance with the memory address and data received from one source until after the completion of a data transfer operation which is in progress in accordance with the memory address and data received from the other source.

Claim 61

A memory for operating in a stacking mode comprising a plurality of storage locations each having a respective access address, a plurality of data lines, means for transferring data between said data lines and a selected one of said storage locations having a derived access address, a plurality of address lines for receiving thereon memory addresses having a plurality of bits therein, a plurality of pointer means each for representing the access address of a storage location, means for storing access addresses in said plurality of pointer means, a group of memory addresses being associated with each of said pointer means, and means for deriving from a received memory address the access address of a selected storage location for use by said data transferring means by performing a predetermined operation on the access address represented by the associated pointer means in accordance with the values of at least some of the bits in the received memory address.

Claim 62

A memory for operating in a stacking mode comprising a plurality of storage locations each having a respective access address, a plurality of data lines, means for transferring data between said data lines and a selected one of said storage locations having a derived access address, a plurality of address lines for receiving thereon memory addresses having a plurality of bits therein, a plurality of pointer means each for representing the access address of a storage location, means for storing access addresses in said plurality of pointer means, a group of memory addresses being associated with each of said pointer means, and means for deriving from a received memory address the access address of a selected storage location for use by said data transferring means by performing a predetermined operation on the access address represented by the associated pointer means in accordance with the values of at least some of the bits in the received memory address.

Claim 63

A memory in accordance with claim 58 wherein responsive to the receipt of at least some of the memory addresses in each of the groups said deriving means uses the access address represented by the associated pointer means as the access address of a storage location.

Claim 64

A memory in accordance with claim 59 further including means for modifying by a predetermined amount the access address used by said data transferring means and storing the modified access address in its previous pointer means.

Claim 65

A memory in accordance with claim 60 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said deriving means increments the access address represented by the associated pointer means by 1.

Claim 66

A memory in accordance with claim 60 wherein responsive to the receipt of at least one of the memory addresses in each of said groups said deriving means increments the access address represented by the associated pointer means by 2.

Claim 67

A memory in accordance with claim 58 wherein responsive to the receipt of at least one of the memory addresses in each of the groups said deriving means increments the access address represented by the associated pointer means by 1.

Claim 68

A memory in accordance with claim 58 wherein responsive to the receipt of at least one of the memory addresses in each of the groups said deriving means increments the access address represented by the associated pointer means by 2.

Claim 69

A memory in accordance with claim 58 wherein responsive to the receipt of at least one of the memory addresses in each of the groups said deriving means modifies by a predetermined amount the access address represented by the associated pointer means to derive an access address of a storage location.

Claim 70

A memory in accordance with claim 65 wherein the access address which is modified is used by said data transferring means, and further including means for storing the modified access address in its previous pointer means.

Claim 71

A memory in accordance with claim 66 wherein responsive to the receipt of at least one of the memory addresses in each of said groups the access address which is modified is decremented by 1.

Claim 72

A memory in accordance with claim 66 wherein responsive to the receipt of at least one of the memory addresses in each of said groups the access address which is modified is decremented by 2.

Claim 73

A memory in accordance with claim 65 wherein responsive to the receipt of at least one of the memory addresses in each of said groups the access address which is modified and used by said data transferring means is left unchanged in its pointer means.

Claim 74

A memory in accordance with claim 69 wherein responsive to the receipt of at least one of the memory addresses in each of said groups the access address which is modified and used by said data transferring means is decremented by 1.

Claim 75

A memory in accordance with claim 69 wherein responsive to the receipt of at least one of the memory addresses in each of said groups the access address which is modified and used by said data transferring means is decremented by 2.

Claim 76

A memory in accordance with claim 58 wherein responsive to the receipt of at least one of the memory addresses in each of the groups said deriving means decrements the access address represented by the associated pointer means by 1.

Claim 77

A memory in accordance with claim 58 wherein responsive to the receipt of at least one of the memory addresses in each of the groups said deriving means decrements the access address represented by the associated pointer means by 2.

Claim 78

A memory in accordance with claim 58 further including means for setting the memory addresses contained in the groups associated with said pointer means.

Claim 79

A memory in accordance with claim 58 wherein memory adDresses and data are received on said plurality of address and data lines from two sources, and further including means for delaying a data transfer operation in accordance with the memory address and data received from one source until after the completion of a data transfer operation which is in progress in accordance with the memory address and data received from the other source.

Claim 80

A memory in accordance with claim 58 further including a plurality of storage means, and means responsive to the receipt of a predetermined memory address on said address lines for controlling the tranfer of data from said data lines to said plurality of storage means.

Claim 81

A memory in accordance with claim 76 further including means responsive to data stored in said plurality of storage means for selectively enabling and disabling the operation of said deriving means.

Claim 82

A memory in accordance with claim 76 further including means responsive to data stored in said plurality of storage means for selecting the memory addresses which are contained in at least one of said groups.

Claim 83

A memory in accordance with claim 58 further including means for selectively changing said predetermined operation performed by said deriving means responsive to a received memory address being contained in at least one of said groups.