Virtual addressing method and apparatus

Claim 1

In a digital computer system including memory devices forming a bulk memory and a local memory, wherein locations in any one of a plurality of memory devices making up a said bulk memory may be virtually addressed to provide, on demand during execution of any selected one of a plurality of programs, instructions and operands from different ones of such memory devices for application to, respectively, said local memory and an arithmetic unit included within a processor, the improvement comprising: a. means for storing a set of logical statements as contiguous translation index words on an integral number of pages in one portion of the local memory, each one of such logical statements containing, at least: i. a bulk memory location code field; ii. a local memory page address field; iii. a page or operand code field; and iv. a present or not present code field; b. means, respsonsive to the contents of the code and address fields in each one of the logical statements as such statements are read, for addressing the bulk memory with, alternatively: i. a fetch operand command word containing, at least, a bulk memory address defining the location of an operand to be fetched from bulk memory; or ii. a fetch page of instructions command word containing, at least, a bulk memory page address defining the location of a page of instructions to be fetched from bulk memory; c. means, responsive to each fetch operand command word, for: i. receiving the operand commanded to be fetched from bulk memory; and ii. enabling the arithmetic unit to process the fetched operand; d. means, responsive to each fetch page of instructions command word, for i. receiving the page of instruction commands to be fetched from bulk memory; ii. means, further responsive to each fetch page of instructions command word, for overlaying such page of instructions on a selected page in local memory; iii. means, further responsive to each fetch page of instructions command word, for entering a present code in the p''''present or not present'''' code field of the current logical statement; and iv. means, further responsive to each fetch page of instructions command word, for enabling the arithmetic unit to be operated in accordance with successive ones of the fetched instructions.