Data processing system utilizing control store unit and push down stack for nested subroutines

Claim 3

The method as defined in claim 1 wherein said step of executing a branch to a subroutine is repeated several times before said executing of a return branch occurs.

Claim 4

The method as defined in claim 1 wherein the step of executing a branch to a subroutine includes the step of: enabling a multiplexer by one address field of said microinstruction generated from said control store unit having a first value to select the next current address from said generated microinstruction, and the step of executing a return branch from the subroutine includes: enabling a multiplexer by said one address field of said microinstruction generated from said control store unit having a second value to select the return address in said first register of said push down stack.

Claim 5

A data processing system for executing a routine which accesses a plurality of subroutines, said system comprising: means for providing a sequence of microinstructions, each microinstruction containing address fields to define an address of a microinstruction of said providing means, and command fields to define transfer paths, one type of said microinstruction specifying a branch to said subroutines and a second type of said microinstructions specifying a return from said subroutines; storing means including: a plurality of registers serially intercoupled, one of said plurality of registers being a first end, another of said plurality of registers being a second end, the remaining of said plurality of registers being intermediate said first and said second end, each of said plurality of registers being adapted to hold one return address, first means coupled to said one and said remaining registers and responsive to said providing means for serially propagating the return addresses to said second end of said plurality of registers and, second means coupled to said second end and said remaining registers and responsive to said providing means for serially propagating the return addresses to said first end of said plurality of registers, wherein said storing means is responsive to said one type of microinstruction for sequentially storing return addresses of previous routines and subroutines in said one register; and means responsive to a series of said second type microinstruction for sequentially transferring to said providing means from said one register of said storing means in a reverse order said return addresses.

Claim 6

A data processing system for executing a routine which accesses a plurality of subroutines, said system comprising: means for providing a sequence of microinstructions, each microinstruction containing address fields to define an address of a microinstruction of said providing means, and command fields to define transfer paths, one type of said microinstruction specifying a branch to said subroutines and a second type of said microinstructions specifying a return from said subroutines; storing means including: a plurality of registers serially intercoupled, one of said plurality of registers being a first end, another of said plurality of registers being a second end, the remaining of said plurality of registers being intermediate said first and said second end, each of said plurality of registers being adapted to hold one return address, first means coupled to said one and said remaining registers and responsive to said providing means for serially propagating the return addresses to said second end of said plurality of registers and, second means coupled to said second end and said remaining registers and responsive to said providing means for serially propagating the return addresses to said first end of said plurality of registers, wherein said storing means is responsive to said one type of microinstruction for sequentially storing return addresses of previous routines and subroutines in said one register; and means responsive to a series of said second type microinstruction for sequentially transferring to said providing means from said one register of said storing means in a reverse order said return addresses.

Claim 7

A system as defined in claim 4 wherein one of said address fields of said providing means has a first value for enabling said storing means to receive said return addresses from said transferring means and a second value for enabling said storing means to deliver said return addresses to said transferring means.

Claim 8

A system as defined in claim 5 and further including: means for incrementing said address of said providing means by a predetermined number, and wherein said one register receives said incremented address from said incrementer means in response to said one command field.

Claim 9

A data processing system for sequentially accessing routines and subroutines, said system comprising: means for providing a sequence of microinstructions, each microinstruction containing address fields to define a next address of a microinstruction of said providing means and command fields to define transfer paths, one of said address fields having a first value which specifies a branch from said subroutines and a second value which specifies a return to said subroutines, one of said command fields specifying a transfer of return addresses; means for receiving an address from said providing means, said address in said receiving means being a present address; storing means including: a plurality of registers serially intercoupled, one of said plurality of registers being a first end, another of said plurality of registers being a second end, the remaining of said plurality of registers being intermediate said first and said second end, each of said plurality of registers being adapted to hold one return address, first means coupled to said one and said remaining registers and responsive to said one address field having a first value of said providing means for serially propagating the return addresses to said second end of said plurality of registers, second means coupled to said second end and said remaining registers and responsive to said one address field having a second value for serially propagating the return addresses to said first end of said plurality of registers, said one register receiving said return address in response to said one address field having a first value and to said one command field; and means responsive to said one address field having said second value for transferring the return address from said one register to said receiving means, said return address becoming said present address.

Claim 10

A data processing system for sequentially accessing routines and subroutines, said system comprising: means for providing a sequence of microinstructions, each microinstruction containing address fields to define a next address of a microinstruction of said providing means and command fields to define transfer paths, one of said address fields having a first value which specifies a branch from said subroutines and a second value which specifies a return to said subroutines, one of said command fields specifying a transfer of return addresses; means for receiving an address from said providing means, said address in said receiving means being a present address; storing means including: a plurality of registers serially intercoupled, one of said plurality of registers being a first end, another of said plurality of registers being a second end, the remaining of said plurality of registers being intermediate said first and said second end, each of said plurality of registers being adapted to hold one return address, first means coupled to said one and said remaining registers and responsive to said one address field having a first value of said providing means for serially propagating the return addresses to said second end of said plurality of registers, second means coupled to said second end and said remaining registers and responsive to said one address field having a second value for serially propagating the return addresses to said first end of said plurality of registers, said one register receiving said return address in response to said one address field having a first value and to said one command field; and means responsive to said one address field having said second value for transferring the return address from said one register to said receiving means, said return address becoming said present address.

Claim 11

A system as defined in claim 7 and further including: incrementer means coupled to said receiving means for incrementing by a predetermined number said present address, said one command field enabling said incremented present address to be transferred to said one register, said incremented address being a return address.

Claim 12

A system as defined in claim 7 wherein said storing means further includes: first means responsive to the absence of said one command field, said one address field having a first value and a master clear signal for holding said return addresses contained in said one and said remaining registers of said plurality of registers, and second means responsive to the absence of said command field and said master clear signal for holding the contents of said return addresses in said another and said remaining registers.

Claim 13

A system as defined in claim 9 wherein said providing means includes: an output register coupled to said storing means for receiving said next address fields and said next command fields, first decoding means coupled to said output register and responsive to said one command field for enabling said first means, and second decoding means coupled to said output register and responsive to said one address field having the second value for enabling said second means.

Claim 14

A system as defined in claim 10 wherein said one address field having a first value and said one command field is provided in a microinstruction branching from said subroutines and wherein said one address field having the second value is provided in said last microinstruction of said subroutines.